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275 lines
9.1 KiB
C++
275 lines
9.1 KiB
C++
//===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains support for writing dwarf debug info into asm files.
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//
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//===----------------------------------------------------------------------===//
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#include "DwarfExpression.h"
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#include "DwarfDebug.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/Support/Dwarf.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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void DwarfExpression::AddReg(int DwarfReg, const char *Comment) {
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assert(DwarfReg >= 0 && "invalid negative dwarf register number");
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if (DwarfReg < 32) {
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EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
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} else {
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EmitOp(dwarf::DW_OP_regx, Comment);
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EmitUnsigned(DwarfReg);
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}
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}
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void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
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assert(DwarfReg >= 0 && "invalid negative dwarf register number");
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if (DwarfReg < 32) {
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EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
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} else {
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EmitOp(dwarf::DW_OP_bregx);
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EmitUnsigned(DwarfReg);
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}
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EmitSigned(Offset);
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if (Deref)
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EmitOp(dwarf::DW_OP_deref);
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}
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void DwarfExpression::AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
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assert(SizeInBits > 0 && "piece has size zero");
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const unsigned SizeOfByte = 8;
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if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
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EmitOp(dwarf::DW_OP_bit_piece);
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EmitUnsigned(SizeInBits);
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EmitUnsigned(OffsetInBits);
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} else {
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EmitOp(dwarf::DW_OP_piece);
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unsigned ByteSize = SizeInBits / SizeOfByte;
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EmitUnsigned(ByteSize);
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}
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}
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void DwarfExpression::AddShr(unsigned ShiftBy) {
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EmitOp(dwarf::DW_OP_constu);
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EmitUnsigned(ShiftBy);
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EmitOp(dwarf::DW_OP_shr);
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}
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bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
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if (isFrameRegister(MachineReg)) {
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// If variable offset is based in frame register then use fbreg.
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EmitOp(dwarf::DW_OP_fbreg);
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EmitSigned(Offset);
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return true;
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}
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int DwarfReg = TRI.getDwarfRegNum(MachineReg, false);
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if (DwarfReg < 0)
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return false;
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AddRegIndirect(DwarfReg, Offset);
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return true;
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}
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bool DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
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unsigned PieceSizeInBits,
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unsigned PieceOffsetInBits) {
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if (!TRI.isPhysicalRegister(MachineReg))
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return false;
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int Reg = TRI.getDwarfRegNum(MachineReg, false);
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// If this is a valid register number, emit it.
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if (Reg >= 0) {
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AddReg(Reg);
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if (PieceSizeInBits)
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AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
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return true;
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}
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// Walk up the super-register chain until we find a valid number.
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// For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
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for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
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Reg = TRI.getDwarfRegNum(*SR, false);
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if (Reg >= 0) {
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unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
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unsigned Size = TRI.getSubRegIdxSize(Idx);
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unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
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AddReg(Reg, "super-register");
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if (PieceOffsetInBits == RegOffset) {
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AddOpPiece(Size, RegOffset);
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} else {
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// If this is part of a variable in a sub-register at a
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// non-zero offset, we need to manually shift the value into
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// place, since the DW_OP_piece describes the part of the
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// variable, not the position of the subregister.
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if (RegOffset)
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AddShr(RegOffset);
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AddOpPiece(Size, PieceOffsetInBits);
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}
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return true;
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}
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}
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// Otherwise, attempt to find a covering set of sub-register numbers.
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// For example, Q0 on ARM is a composition of D0+D1.
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//
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// Keep track of the current position so we can emit the more
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// efficient DW_OP_piece.
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unsigned CurPos = PieceOffsetInBits;
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// The size of the register in bits, assuming 8 bits per byte.
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unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
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// Keep track of the bits in the register we already emitted, so we
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// can avoid emitting redundant aliasing subregs.
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SmallBitVector Coverage(RegSize, false);
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for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
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unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
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unsigned Size = TRI.getSubRegIdxSize(Idx);
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unsigned Offset = TRI.getSubRegIdxOffset(Idx);
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Reg = TRI.getDwarfRegNum(*SR, false);
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// Intersection between the bits we already emitted and the bits
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// covered by this subregister.
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SmallBitVector Intersection(RegSize, false);
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Intersection.set(Offset, Offset + Size);
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Intersection ^= Coverage;
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// If this sub-register has a DWARF number and we haven't covered
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// its range, emit a DWARF piece for it.
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if (Reg >= 0 && Intersection.any()) {
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AddReg(Reg, "sub-register");
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AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
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CurPos = Offset + Size;
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// Mark it as emitted.
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Coverage.set(Offset, Offset + Size);
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}
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}
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return CurPos > PieceOffsetInBits;
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}
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void DwarfExpression::AddSignedConstant(int Value) {
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EmitOp(dwarf::DW_OP_consts);
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EmitSigned(Value);
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// The proper way to describe a constant value is
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// DW_OP_constu <const>, DW_OP_stack_value.
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// Unfortunately, DW_OP_stack_value was not available until DWARF-4,
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// so we will continue to generate DW_OP_constu <const> for DWARF-2
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// and DWARF-3. Technically, this is incorrect since DW_OP_const <const>
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// actually describes a value at a constant addess, not a constant value.
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// However, in the past there was no better way to describe a constant
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// value, so the producers and consumers started to rely on heuristics
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// to disambiguate the value vs. location status of the expression.
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// See PR21176 for more details.
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if (DwarfVersion >= 4)
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EmitOp(dwarf::DW_OP_stack_value);
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}
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void DwarfExpression::AddUnsignedConstant(unsigned Value) {
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EmitOp(dwarf::DW_OP_constu);
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EmitUnsigned(Value);
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// cf. comment in DwarfExpression::AddSignedConstant().
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if (DwarfVersion >= 4)
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EmitOp(dwarf::DW_OP_stack_value);
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}
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static unsigned getOffsetOrZero(unsigned OffsetInBits,
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unsigned PieceOffsetInBits) {
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if (OffsetInBits == PieceOffsetInBits)
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return 0;
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assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces");
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return OffsetInBits;
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}
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bool DwarfExpression::AddMachineRegExpression(const DIExpression *Expr,
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unsigned MachineReg,
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unsigned PieceOffsetInBits) {
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auto I = Expr->expr_op_begin();
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auto E = Expr->expr_op_end();
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if (I == E)
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return AddMachineRegPiece(MachineReg);
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// Pattern-match combinations for which more efficient representations exist
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// first.
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bool ValidReg = false;
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switch (I->getOp()) {
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case dwarf::DW_OP_bit_piece: {
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unsigned OffsetInBits = I->getArg(0);
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unsigned SizeInBits = I->getArg(1);
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// Piece always comes at the end of the expression.
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return AddMachineRegPiece(MachineReg, SizeInBits,
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getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
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}
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case dwarf::DW_OP_plus:
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case dwarf::DW_OP_minus: {
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// [DW_OP_reg,Offset,DW_OP_plus, DW_OP_deref] --> [DW_OP_breg, Offset].
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// [DW_OP_reg,Offset,DW_OP_minus,DW_OP_deref] --> [DW_OP_breg,-Offset].
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auto N = I.getNext();
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if (N != E && N->getOp() == dwarf::DW_OP_deref) {
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unsigned Offset = I->getArg(0);
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ValidReg = AddMachineRegIndirect(
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MachineReg, I->getOp() == dwarf::DW_OP_plus ? Offset : -Offset);
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std::advance(I, 2);
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break;
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} else
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ValidReg = AddMachineRegPiece(MachineReg);
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}
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case dwarf::DW_OP_deref: {
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// [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
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ValidReg = AddMachineRegIndirect(MachineReg);
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++I;
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break;
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}
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default:
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llvm_unreachable("unsupported operand");
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}
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if (!ValidReg)
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return false;
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// Emit remaining elements of the expression.
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AddExpression(I, E, PieceOffsetInBits);
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return true;
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}
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void DwarfExpression::AddExpression(DIExpression::expr_op_iterator I,
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DIExpression::expr_op_iterator E,
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unsigned PieceOffsetInBits) {
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for (; I != E; ++I) {
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switch (I->getOp()) {
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case dwarf::DW_OP_bit_piece: {
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unsigned OffsetInBits = I->getArg(0);
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unsigned SizeInBits = I->getArg(1);
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AddOpPiece(SizeInBits, getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
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break;
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}
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case dwarf::DW_OP_plus:
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EmitOp(dwarf::DW_OP_plus_uconst);
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EmitUnsigned(I->getArg(0));
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break;
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case dwarf::DW_OP_minus:
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// There is no OP_minus_uconst.
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EmitOp(dwarf::DW_OP_constu);
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EmitUnsigned(I->getArg(0));
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EmitOp(dwarf::DW_OP_minus);
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break;
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case dwarf::DW_OP_deref:
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EmitOp(dwarf::DW_OP_deref);
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break;
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default:
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llvm_unreachable("unhandled opcode found in expression");
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}
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}
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}
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