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524 lines
21 KiB
TableGen
524 lines
21 KiB
TableGen
//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction aliases for Sparc.
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//===----------------------------------------------------------------------===//
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// Instruction aliases for conditional moves.
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// mov<cond> <ccreg> rs2, rd
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multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
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Instruction movrr, Instruction movri,
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Instruction fmovs, Instruction fmovd> {
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// mov<cond> (%icc|%xcc), rs2, rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
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", $rs2, $rd"),
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(movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
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// mov<cond> (%icc|%xcc), simm11, rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
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", $simm11, $rd"),
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(movri IntRegs:$rd, i32imm:$simm11, condVal)>;
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// fmovs<cond> (%icc|%xcc), $rs2, $rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
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", $rs2, $rd"),
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(fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
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// fmovd<cond> (%icc|%xcc), $rs2, $rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
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", $rs2, $rd"),
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(fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
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}
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// mov<cond> <ccreg> rs2, rd
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multiclass fpcond_mov_alias<string cond, int condVal,
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Instruction movrr, Instruction movri,
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Instruction fmovs, Instruction fmovd> {
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// mov<cond> %fcc[0-3], rs2, rd
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def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
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(movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
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// mov<cond> %fcc[0-3], simm11, rd
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def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
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(movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
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// fmovs<cond> %fcc[0-3], $rs2, $rd
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def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
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(fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
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// fmovd<cond> %fcc[0-3], $rs2, $rd
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def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
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(fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
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}
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// Instruction aliases for integer conditional branches and moves.
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multiclass int_cond_alias<string cond, int condVal> {
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// b<cond> $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
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(BCOND brtarget:$imm, condVal)>;
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// b<cond>,a $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
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(BCONDA brtarget:$imm, condVal)>;
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// b<cond> %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
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(BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond>,pt %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
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(BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond>,a %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
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(BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond>,a,pt %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
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(BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond>,pn %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
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(BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond>,a,pn %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
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(BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond> %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
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(BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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// b<cond>,pt %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
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(BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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// b<cond>,a %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
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(BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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// b<cond>,a,pt %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
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(BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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// b<cond>,pn %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
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(BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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// b<cond>,a,pn %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
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(BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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defm : intcond_mov_alias<cond, condVal, " %icc",
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MOVICCrr, MOVICCri,
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FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
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defm : intcond_mov_alias<cond, condVal, " %xcc",
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MOVXCCrr, MOVXCCri,
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FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
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// fmovq<cond> (%icc|%xcc), $rs2, $rd
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def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
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(FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
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Requires<[HasV9, HasHardQuad]>;
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def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
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(FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
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Requires<[Is64Bit, HasHardQuad]>;
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// t<cond> %icc, rs => t<cond> %icc, G0 + rs
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def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),
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(TICCrr G0, IntRegs:$rs2, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %icc, rs1 + rs2
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def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
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(TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
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def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),
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(TXCCrr G0, IntRegs:$rs2, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %xcc, rs1 + rs2
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def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
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(TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
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Requires<[HasV9]>;
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// t<cond> rs=> t<cond> %icc, G0 + rs2
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//def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),
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// (TICCrr G0, IntRegs:$rs2, condVal)>,
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// Requires<[HasV9]>;
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// t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
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//def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
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// (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
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// Requires<[HasV9]>;
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// t<cond> %icc, imm => t<cond> %icc, G0 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),
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(TICCri G0, i32imm:$imm, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %icc, rs1 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
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(TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),
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(TXCCri G0, i32imm:$imm, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %xcc, rs1 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
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(TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
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Requires<[HasV9]>;
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// t<cond> imm => t<cond> G0 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),
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(TRAPri G0, i32imm:$imm, condVal)>;
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// t<cond> rs1 + imm => t<cond> rs1 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
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(TRAPri IntRegs:$rs1, i32imm:$imm, condVal)>;
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// t<cond> rs1 => t<cond> G0 + rs1
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def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1"),
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(TRAPrr G0, IntRegs:$rs1, condVal)>;
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// t<cond> rs1 + rs2
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def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
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(TRAPrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
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}
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// Instruction aliases for floating point conditional branches and moves.
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multiclass fp_cond_alias<string cond, int condVal> {
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// fb<cond> $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
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(FBCOND brtarget:$imm, condVal), 0>;
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// fb<cond>,a $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
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(FBCONDA brtarget:$imm, condVal), 0>;
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// fb<cond> %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
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(BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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// fb<cond>,pt %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
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(BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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// fb<cond>,a %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
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(BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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// fb<cond>,a,pt %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
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(BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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// fb<cond>,pn %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
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(BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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// fb<cond>,a,pn %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
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(BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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defm : fpcond_mov_alias<cond, condVal,
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V9MOVFCCrr, V9MOVFCCri,
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V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
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// fmovq<cond> %fcc0, $rs2, $rd
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def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
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(V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
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condVal)>,
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Requires<[HasV9, HasHardQuad]>;
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}
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// Instruction aliases for co-processor conditional branches.
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multiclass cp_cond_alias<string cond, int condVal> {
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// cb<cond> $imm
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def : InstAlias<!strconcat(!strconcat("cb", cond), " $imm"),
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(CBCOND brtarget:$imm, condVal), 0>;
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// cb<cond>,a $imm
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def : InstAlias<!strconcat(!strconcat("cb", cond), ",a $imm"),
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(CBCONDA brtarget:$imm, condVal), 0>;
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}
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defm : int_cond_alias<"a", 0b1000>;
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defm : int_cond_alias<"n", 0b0000>;
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defm : int_cond_alias<"ne", 0b1001>;
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defm : int_cond_alias<"e", 0b0001>;
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defm : int_cond_alias<"g", 0b1010>;
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defm : int_cond_alias<"le", 0b0010>;
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defm : int_cond_alias<"ge", 0b1011>;
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defm : int_cond_alias<"l", 0b0011>;
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defm : int_cond_alias<"gu", 0b1100>;
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defm : int_cond_alias<"leu", 0b0100>;
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defm : int_cond_alias<"cc", 0b1101>;
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defm : int_cond_alias<"cs", 0b0101>;
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defm : int_cond_alias<"pos", 0b1110>;
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defm : int_cond_alias<"neg", 0b0110>;
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defm : int_cond_alias<"vc", 0b1111>;
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defm : int_cond_alias<"vs", 0b0111>;
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let EmitPriority = 0 in
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{
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defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
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defm : int_cond_alias<"nz", 0b1001>; // same as ne
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defm : int_cond_alias<"eq", 0b0001>; // same as e
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defm : int_cond_alias<"z", 0b0001>; // same as e
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defm : int_cond_alias<"geu", 0b1101>; // same as cc
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defm : int_cond_alias<"lu", 0b0101>; // same as cs
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}
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defm : fp_cond_alias<"a", 0b1000>;
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defm : fp_cond_alias<"n", 0b0000>;
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defm : fp_cond_alias<"u", 0b0111>;
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defm : fp_cond_alias<"g", 0b0110>;
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defm : fp_cond_alias<"ug", 0b0101>;
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defm : fp_cond_alias<"l", 0b0100>;
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defm : fp_cond_alias<"ul", 0b0011>;
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defm : fp_cond_alias<"lg", 0b0010>;
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defm : fp_cond_alias<"ne", 0b0001>;
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defm : fp_cond_alias<"e", 0b1001>;
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defm : fp_cond_alias<"ue", 0b1010>;
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defm : fp_cond_alias<"ge", 0b1011>;
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defm : fp_cond_alias<"uge", 0b1100>;
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defm : fp_cond_alias<"le", 0b1101>;
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defm : fp_cond_alias<"ule", 0b1110>;
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defm : fp_cond_alias<"o", 0b1111>;
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let EmitPriority = 0 in
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{
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defm : fp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
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defm : fp_cond_alias<"nz", 0b0001>; // same as ne
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defm : fp_cond_alias<"z", 0b1001>; // same as e
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}
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defm : cp_cond_alias<"a", 0b1000>;
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defm : cp_cond_alias<"n", 0b0000>;
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defm : cp_cond_alias<"3", 0b0111>;
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defm : cp_cond_alias<"2", 0b0110>;
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defm : cp_cond_alias<"23", 0b0101>;
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defm : cp_cond_alias<"1", 0b0100>;
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defm : cp_cond_alias<"13", 0b0011>;
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defm : cp_cond_alias<"12", 0b0010>;
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defm : cp_cond_alias<"123", 0b0001>;
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defm : cp_cond_alias<"0", 0b1001>;
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defm : cp_cond_alias<"03", 0b1010>;
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defm : cp_cond_alias<"02", 0b1011>;
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defm : cp_cond_alias<"023", 0b1100>;
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defm : cp_cond_alias<"01", 0b1101>;
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defm : cp_cond_alias<"013", 0b1110>;
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defm : cp_cond_alias<"012", 0b1111>;
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let EmitPriority = 0 in defm : cp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
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// Section A.3 Synthetic Instructions
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// Most are marked as Emit=0, so that they are not used for disassembly. This is
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// an aesthetic issue, but the chosen policy is to typically prefer using the
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// non-alias form, except for the most obvious and clarifying aliases: cmp, jmp,
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// call, tst, ret, retl.
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// Note: cmp is handled in SparcInstrInfo.
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// jmp/call/ret/retl have special case handling for output in
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// SparcInstPrinter.cpp
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// jmp addr -> jmpl addr, %g0
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def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
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def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
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// call addr -> jmpl addr, %o7
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def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
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def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
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// tst reg -> orcc %g0, reg, %g0
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def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>;
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// ret -> jmpl %i7+8, %g0 (aka RET 8)
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def : InstAlias<"ret", (RET 8)>;
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// retl -> jmpl %o7+8, %g0 (aka RETL 8)
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def : InstAlias<"retl", (RETL 8)>;
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// restore -> restore %g0, %g0, %g0
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def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
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// save -> restore %g0, %g0, %g0
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def : InstAlias<"save", (SAVErr G0, G0, G0)>;
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// set value, rd
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// (turns into a sequence of sethi+or, depending on the value)
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// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
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def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
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// not rd -> xnor rd, %g0, rd
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def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
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// not reg, rd -> xnor reg, %g0, rd
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def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
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// neg rd -> sub %g0, rd, rd
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def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
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// neg reg, rd -> sub %g0, reg, rd
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def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
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// inc rd -> add rd, 1, rd
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def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
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// inc simm13, rd -> add rd, simm13, rd
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def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// inccc rd -> addcc rd, 1, rd
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def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
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// inccc simm13, rd -> addcc rd, simm13, rd
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def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// dec rd -> sub rd, 1, rd
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def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
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// dec simm13, rd -> sub rd, simm13, rd
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def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// deccc rd -> subcc rd, 1, rd
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def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
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// deccc simm13, rd -> subcc rd, simm13, rd
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def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0
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def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;
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def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
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// bset reg_or_imm, rd -> or rd,reg_or_imm,rd
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def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
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def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
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def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
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def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
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def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
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def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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// clr rd -> or %g0, %g0, rd
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def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>;
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// clr{b,h,} [addr] -> st{b,h,} %g0, [addr]
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def : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>;
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def : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>;
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def : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>;
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def : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>;
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def : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>;
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def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;
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// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
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def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
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def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
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// mov specialreg, rd -> rd specialreg, rd
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def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
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def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
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def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
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def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
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// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
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def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
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def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
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def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
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def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
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def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
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// End of Section A.3
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// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
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// (aka: omit the first arg when it's g0. This is not in the manual, but is
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// supported by gnu and solaris as)
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def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
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def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
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def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
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def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
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def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
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def : InstAlias<"pwr $rs2, %psr", (PWRPSRrr G0, IntRegs:$rs2), 0>;
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def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, i32imm:$simm13), 0>;
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// flush -> flush %g0
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def : InstAlias<"flush", (FLUSH), 0>;
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// unimp -> unimp 0
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def : InstAlias<"unimp", (UNIMP 0), 0>;
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def : MnemonicAlias<"iflush", "flush">;
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def : MnemonicAlias<"stub", "stb">;
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def : MnemonicAlias<"stsb", "stb">;
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def : MnemonicAlias<"stuba", "stba">;
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def : MnemonicAlias<"stsba", "stba">;
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def : MnemonicAlias<"stuh", "sth">;
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def : MnemonicAlias<"stsh", "sth">;
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def : MnemonicAlias<"stuha", "stha">;
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def : MnemonicAlias<"stsha", "stha">;
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def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>;
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def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>;
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def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
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def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
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def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
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def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
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def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
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def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
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def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
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def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
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Requires<[HasHardQuad]>;
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def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
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def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
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DFPRegs:$rs2)>;
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def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
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QFPRegs:$rs2)>,
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Requires<[HasHardQuad]>;
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// signx rd -> sra rd, %g0, rd
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def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;
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// signx reg, rd -> sra reg, %g0, rd
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def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;
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