1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/test/CodeGen/Mips/msa
Daniel Sanders 6fac4ec6e5 [mips][msa] Remove copy_u.d and move copy_u.w to MSA64.
Summary:
The forwards compatibility strategy employed by MIPS is to consider registers
to be infinitely sign-extended. Then on ISA's with a wider register, the result
of existing instructions are sign-extended to register width and zero-extended
counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this
strategy and we have therefore corrected the MSA specs to fix this.

We still keep track of sign/zero-extension during legalization but we now
match copy_s.[wd] where required.

No change required to clang since __builtin_msa_copy_u_[wd] will map to
copy_s.[wd] where appropriate for the target.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13472

llvm-svn: 250887
2015-10-21 09:58:54 +00:00
..
2r_vector_scalar.ll
2r.ll
2rf_exup.ll
2rf_float_int.ll
2rf_fq.ll
2rf_int_float.ll
2rf_tq.ll
2rf.ll
3r_4r_widen.ll
3r_4r.ll
3r_splat.ll
3r-a.ll
3r-b.ll
3r-c.ll
3r-d.ll
3r-i.ll
3r-m.ll
3r-p.ll
3r-s.ll
3r-v.ll
3rf_4rf_q.ll
3rf_4rf.ll
3rf_exdo.ll
3rf_float_int.ll
3rf_int_float.ll
3rf_q.ll
3rf.ll
arithmetic_float.ll
arithmetic.ll
basic_operations_float.ll [mips] Generate code for insert/extract operations when using the N64 ABI and MSA. 2015-05-05 10:32:24 +00:00
basic_operations.ll [mips] Generate code for insert/extract operations when using the N64 ABI and MSA. 2015-05-05 10:32:24 +00:00
bit.ll
bitcast.ll
bitwise.ll
compare_float.ll
compare.ll
elm_copy.ll [mips][msa] Remove copy_u.d and move copy_u.w to MSA64. 2015-10-21 09:58:54 +00:00
elm_cxcmsa.ll
elm_insv.ll
elm_move.ll
elm_shift_slide.ll
endian.ll
frameindex.ll
i5_ld_st.ll
i5-a.ll
i5-b.ll
i5-c.ll
i5-m.ll
i5-s.ll
i8.ll
i10.ll
inline-asm.ll
llvm-stress-s449609655-simplified.ll
llvm-stress-s525530439.ll
llvm-stress-s997348632.ll
llvm-stress-s1704963983.ll
llvm-stress-s1935737938.ll
llvm-stress-s2090927243-simplified.ll
llvm-stress-s2501752154-simplified.ll
llvm-stress-s2704903805.ll
llvm-stress-s3861334421.ll
llvm-stress-s3926023935.ll
llvm-stress-s3997499501.ll
llvm-stress-sz1-s742806235.ll
shift-dagcombine.ll
shuffle.ll [mips] Correct and improve special-case shuffle instructions. 2015-05-19 12:24:52 +00:00
special.ll
spill.ll
vec.ll
vecs10.ll