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ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
51 lines
1.9 KiB
LLVM
51 lines
1.9 KiB
LLVM
; Test the MSA floating-point to fixed-point conversion intrinsics that are
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; encoded with the 2RF instruction format.
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
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@llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_ftq_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
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@llvm_mips_ftq_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_ftq_h_test() nounwind {
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entry:
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%0 = load <4 x float>, <4 x float>* @llvm_mips_ftq_h_ARG1
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%1 = load <4 x float>, <4 x float>* @llvm_mips_ftq_h_ARG2
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%2 = tail call <8 x i16> @llvm.mips.ftq.h(<4 x float> %0, <4 x float> %1)
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store <8 x i16> %2, <8 x i16>* @llvm_mips_ftq_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.ftq.h(<4 x float>, <4 x float>) nounwind
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; CHECK: llvm_mips_ftq_h_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: ftq.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_ftq_h_test
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;
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@llvm_mips_ftq_w_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_ftq_w_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
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@llvm_mips_ftq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_ftq_w_test() nounwind {
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entry:
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%0 = load <2 x double>, <2 x double>* @llvm_mips_ftq_w_ARG1
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%1 = load <2 x double>, <2 x double>* @llvm_mips_ftq_w_ARG2
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%2 = tail call <4 x i32> @llvm.mips.ftq.w(<2 x double> %0, <2 x double> %1)
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store <4 x i32> %2, <4 x i32>* @llvm_mips_ftq_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.ftq.w(<2 x double>, <2 x double>) nounwind
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; CHECK: llvm_mips_ftq_w_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: ftq.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_ftq_w_test
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;
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