Alexandros Lamprineas 7f36d7f86a [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for ... "msr pan, #imm", while only 1-bit immediate values should be valid. Changed encoding and decoding for msr pstate instructions. Differential Revision: http://reviews.llvm.org/D13011 llvm-svn: 249313		2015-10-05 13:42:31 +00:00
..
a64-ignored-fields.txt
arm64-advsimd.txt
arm64-arithmetic.txt
arm64-basic-a64-undefined.txt
arm64-bitfield.txt
arm64-branch.txt
arm64-canonical-form.txt
arm64-crc32.txt
arm64-crypto.txt
arm64-invalid-logical.txt
arm64-logical.txt
arm64-memory.txt
arm64-non-apple-fmov.txt
arm64-scalar-fp.txt
arm64-system.txt
armv8.1a-atomic.txt	AArch64: fix typo in SMIN far atomics and add tests	2015-06-02 18:37:20 +00:00
armv8.1a-lor.txt	[AArch64] LORID_EL1 register must be treated as read-only	2015-04-20 16:54:37 +00:00
armv8.1a-pan.txt	[MC layer][AArch64] llvm-mc accepts 4-bit immediate values for	2015-10-05 13:42:31 +00:00
armv8.1a-rdma.txt
armv8.1a-vhe.txt	[AArch64] Add v8.1a "Virtualization Host Extensions"	2015-04-16 15:38:58 +00:00
basic-a64-instructions.txt	[AArch64] Fix problems in decoding generic MSR instructions	2015-07-15 08:10:30 +00:00
basic-a64-undefined.txt
basic-a64-unpredictable.txt
gicv3-regs.txt
ldp-offset-predictable.txt
ldp-postind.predictable.txt
ldp-preind.predictable.txt
lit.local.cfg
neon-instructions.txt
trace-regs.txt