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02ccf5b7ea
This patch implements the Cortex-A57 scheduling model. The main code is in ARMScheduleA57.td, ARMScheduleA57WriteRes.td. Small changes in cpp,.h files to support required scheduling predicates. Scheduling model implemented according to: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf. Patch by : Andrew Zhogin (submitted on his behalf, as requested). Rewiewed by: Renato Golin, Diana Picus, Javed Absar, Kristof Beyls. Differential Revision: https://reviews.llvm.org/D28152 llvm-svn: 304530
24 lines
694 B
LLVM
24 lines
694 B
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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; CHECK: ********** MI Scheduling **********
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; We need second, post-ra scheduling to have VSTM instruction combined from single-stores
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; CHECK: ********** MI Scheduling **********
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; CHECK: schedule starting
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; CHECK: VSTMDIA
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; CHECK: rdefs left
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; CHECK-NEXT: Latency : 2
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%bigVec = type [2 x double]
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@var = global %bigVec zeroinitializer
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define void @bar(%bigVec* %ptr) {
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%tmp = load %bigVec, %bigVec* %ptr
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store %bigVec %tmp, %bigVec* @var
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ret void
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}
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