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21a7afce23
Enables using the high and high-adjusted symbol modifiers on thread local storage modifers in powerpc assembly. Needed to be able to support 64 bit thread-pointer and dynamic-thread-pointer access sequences. Differential Revision: https://reviews.llvm.org/D47754 llvm-svn: 334856
105 lines
2.8 KiB
ArmAsm
105 lines
2.8 KiB
ArmAsm
// RUN: llvm-mc -triple=powerpc64le-pc-linux -filetype=obj %s -o - | \
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// RUN: llvm-readobj -r | FileCheck %s
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// RUN: llvm-mc -triple=powerpc64-pc-linux -filetype=obj %s -o - | \
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// RUN: llvm-readobj -r | FileCheck %s
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// Verify we can handle all the tprel symbol modifiers for local exec tls.
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// Tests 16 bit offsets on both DS-form and D-form instructions, 32 bit
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// adjusted and non-adjusted offsets and 64 bit adjusted and non-adjusted
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// offsets.
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.text
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.abiversion 2
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.globl short_offset_ds
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.p2align 4
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.type short_offset_ds,@function
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short_offset_ds:
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lwa 3, i@tprel(13)
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blr
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.globl short_offset
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.p2align 4
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.type short_offset,@function
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short_offset:
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addi 3, 13, i@tprel
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blr
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.globl medium_offset
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.p2align 4
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.type medium_offset,@function
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medium_offset:
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addis 3, 13, i@tprel@ha
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lwa 3, i@tprel@l(3)
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blr
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.globl medium_not_adjusted
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.p2align 4
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.type medium_not_adjusted,@function
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medium_not_adjusted:
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lis 3, i@tprel@h
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ori 3, 3, i@tprel@l
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lwax 3, 3, 13
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blr
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.globl large_offset
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.p2align 4
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.type large_offset,@function
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large_offset:
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lis 3, i@tprel@highesta
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ori 3, 3, i@tprel@highera
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sldi 3, 3, 32
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oris 3, 3, i@tprel@higha
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addi 3, 3, i@tprel@l
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lwax 3, 3, 13
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blr
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.globl not_adjusted
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.p2align 4
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.type not_adjusted,@function
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not_adjusted:
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lis 3, i@tprel@highest
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ori 3, 3, i@tprel@higher
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sldi 3, 3, 32
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oris 3, 3, i@tprel@high
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ori 3, 3, i@tprel@l
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lwax 3, 3, 13
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blr
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.type i,@object
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.section .tdata,"awT",@progbits
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.p2align 2
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i:
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.long 55
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.size i, 4
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.type j,@object
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.data
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.p2align 3
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j:
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.quad i@tprel
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.size j, 8
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# CHECK: Relocations [
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# CHECK: Section {{.*}} .rela.text {
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_DS i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16 i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_HA i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_LO_DS i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_HI i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_LO i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_HIGHESTA i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_HIGHERA i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_HIGHA i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_LO i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_HIGHEST i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_HIGHER i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_HIGH i
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL16_LO i
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# CHECK: }
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# CHECK: Section (6) .rela.data {
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# CHECK: 0x{{[0-9A-F]+}} R_PPC64_TPREL64 i
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# CHECK: }
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# CHECK: ]
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