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9008ed7f02
Start by emitting remarks for very basic unsupported cases such as irreducible CFGs and EHFunclets. The end goal is to be able to cover all the cases where we give up with an explanation. llvm-svn: 333972
168 lines
7.8 KiB
LLVM
168 lines
7.8 KiB
LLVM
; RUN: llc -mtriple=arm64-- -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | grep -v "Verify generated machine code" | FileCheck %s
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; REQUIRES: asserts
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; CHECK-LABEL: Pass Arguments:
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; CHECK-NEXT: Target Library Information
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; CHECK-NEXT: Target Pass Configuration
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; CHECK-NEXT: Machine Module Information
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; CHECK-NEXT: Target Transform Information
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; CHECK-NEXT: Assumption Cache Tracker
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; CHECK-NEXT: Type-Based Alias Analysis
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; CHECK-NEXT: Scoped NoAlias Alias Analysis
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; CHECK-NEXT: Create Garbage Collector Module Metadata
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; CHECK-NEXT: Profile summary info
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; CHECK-NEXT: Machine Branch Probability Analysis
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; CHECK-NEXT: ModulePass Manager
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; CHECK-NEXT: Pre-ISel Intrinsic Lowering
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Expand Atomic instructions
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; CHECK-NEXT: Simplify the CFG
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: Optimization Remark Emitter
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Loop Data Prefetch
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; CHECK-NEXT: Falkor HW Prefetch Fix
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: Canonicalize natural loops
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; CHECK-NEXT: Loop Pass Manager
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; CHECK-NEXT: Induction Variable Users
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; CHECK-NEXT: Loop Strength Reduction
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; CHECK-NEXT: Merge contiguous icmps into a memcmp
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; CHECK-NEXT: Expand memcmp() to load/stores
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; CHECK-NEXT: Lower Garbage Collection Instructions
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; CHECK-NEXT: Shadow Stack GC Lowering
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; CHECK-NEXT: Remove unreachable blocks from the CFG
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Branch Probability Analysis
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; CHECK-NEXT: Block Frequency Analysis
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; CHECK-NEXT: Constant Hoisting
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; CHECK-NEXT: Partially inline calls to library functions
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; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
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; CHECK-NEXT: Scalarize Masked Memory Intrinsics
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; CHECK-NEXT: Expand reduction intrinsics
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Interleaved Access Pass
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: CodeGen Prepare
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; CHECK-NEXT: Rewrite Symbols
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Exception handling preparation
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; CHECK-NEXT: AArch64 Promote Constant
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; CHECK-NEXT: Unnamed pass: implement Pass::getPassName()
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Merge internal globals
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; CHECK-NEXT: Safe Stack instrumentation pass
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; CHECK-NEXT: Insert stack protectors
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Branch Probability Analysis
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; CHECK-NEXT: AArch64 Instruction Selection
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: AArch64 Local Dynamic TLS Access Clean-up
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; CHECK-NEXT: Expand ISel Pseudo-instructions
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; CHECK-NEXT: Early Tail Duplication
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; CHECK-NEXT: Optimize machine instruction PHIs
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; CHECK-NEXT: Slot index numbering
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; CHECK-NEXT: Merge disjoint stack slots
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; CHECK-NEXT: Local Stack Slot Allocation
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; CHECK-NEXT: Remove dead machine instructions
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: AArch64 Condition Optimizer
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Trace Metrics
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; CHECK-NEXT: AArch64 Conditional Compares
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; CHECK-NEXT: Machine InstCombiner
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; CHECK-NEXT: AArch64 Conditional Branch Tuning
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; CHECK-NEXT: Machine Trace Metrics
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; CHECK-NEXT: Early If-Conversion
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; CHECK-NEXT: AArch64 Store Pair Suppression
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; CHECK-NEXT: AArch64 SIMD instructions optimization pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Early Machine Loop Invariant Code Motion
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; CHECK-NEXT: Machine Common Subexpression Elimination
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Machine code sinking
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; CHECK-NEXT: Peephole Optimizations
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; CHECK-NEXT: Remove dead machine instructions
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; CHECK-NEXT: AArch64 Dead register definitions
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; CHECK-NEXT: Detect Dead Lanes
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; CHECK-NEXT: Process Implicit Definitions
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; CHECK-NEXT: Remove unreachable machine basic blocks
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; CHECK-NEXT: Live Variable Analysis
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; CHECK-NEXT: Eliminate PHI nodes for register allocation
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; CHECK-NEXT: Two-Address instruction pass
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; CHECK-NEXT: Slot index numbering
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; CHECK-NEXT: Live Interval Analysis
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; CHECK-NEXT: Simple Register Coalescing
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; CHECK-NEXT: Rename Disconnected Subregister Components
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; CHECK-NEXT: Machine Instruction Scheduler
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Debug Variable Analysis
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; CHECK-NEXT: Live Stack Slot Analysis
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; CHECK-NEXT: Virtual Register Map
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; CHECK-NEXT: Live Register Matrix
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; CHECK-NEXT: Bundle Machine CFG Edges
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; CHECK-NEXT: Spill Code Placement Analysis
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Greedy Register Allocator
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; CHECK-NEXT: Virtual Register Rewriter
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; CHECK-NEXT: Stack Slot Coloring
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; CHECK-NEXT: Machine Copy Propagation Pass
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; CHECK-NEXT: Machine Loop Invariant Code Motion
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; CHECK-NEXT: AArch64 Redundant Copy Elimination
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; CHECK-NEXT: A57 FP Anti-dependency breaker
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; CHECK-NEXT: PostRA Machine Sink
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Shrink Wrapping analysis
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; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
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; CHECK-NEXT: Control Flow Optimizer
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; CHECK-NEXT: Tail Duplication
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; CHECK-NEXT: Machine Copy Propagation Pass
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; CHECK-NEXT: Post-RA pseudo instruction expansion pass
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; CHECK-NEXT: AArch64 pseudo instruction expansion pass
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; CHECK-NEXT: AArch64 load / store optimization pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Falkor HW Prefetch Fix Late Phase
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; CHECK-NEXT: PostRA Machine Instruction Scheduler
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; CHECK-NEXT: Analyze Machine Code For Garbage Collection
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Branch Probability Basic Block Placement
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; CHECK-NEXT: Branch relaxation pass
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; CHECK-NEXT: Contiguously Lay Out Funclets
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; CHECK-NEXT: StackMap Liveness Analysis
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; CHECK-NEXT: Live DEBUG_VALUE analysis
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; CHECK-NEXT: Insert fentry calls
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; CHECK-NEXT: Insert XRay ops
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; CHECK-NEXT: Implement the 'patchable-function' attribute
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: AArch64 Assembly Printer
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; CHECK-NEXT: Free MachineFunction
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; CHECK-NEXT: Pass Arguments: -domtree
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Dominator Tree Construction
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define void @f() {
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ret void
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}
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