Andrea Di Biagio 13160fb6a6 [MCA][LSUnit] Track loads and stores until retirement. ... Before this patch, loads and stores were only tracked by their corresponding queues in the LSUnit from dispatch until execute stage. In practice we should be more conservative and assume that memory opcodes leave their queues at retirement stage. Basically, loads should leave the load queue only when they have completed and delivered their data. We conservatively assume that a load is completed when it is retired. Stores should be tracked by the store queue from dispatch until retirement. In practice, stores can only leave the store queue if their data can be written to the data cache. This is mostly a mechanical change. With this patch, the retire stage notifies the LSUnit when a memory instruction is retired. That would triggers the release of LDQ/STQ entries. The only visible change is in memory tests for the bdver2 model. That is because bdver2 is the only model that defines the load/store queue size. This patch partially addresses PR39830. Differential Revision: https://reviews.llvm.org/D68266 llvm-svn: 374034		2019-10-08 10:46:01 +00:00
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HardwareUnits	[MCA][LSUnit] Track loads and stores until retirement.	2019-10-08 10:46:01 +00:00
Stages	[MCA][LSUnit] Track loads and stores until retirement.	2019-10-08 10:46:01 +00:00
CodeEmitter.h
Context.h
HWEventListener.h
InstrBuilder.h
Instruction.h	[MCA] consistently use MCPhysReg instead of unsigned as register type. NFCI	2019-08-22 13:32:17 +00:00
Pipeline.h
SourceMgr.h	[MCA] Fix MSVC 19.16 build with libc++	2019-08-09 12:41:24 +00:00
Support.h