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llvm-mirror/test/CodeGen/PowerPC/scalar_vector_test_4.ll
QingShan Zhang 2f3956c41c [Power9] Enable the Out-of-Order scheduling model for P9 hw 
When switched to the MI scheduler for P9, the hardware is modeled as out of order.
However, inside the MI Scheduler algorithm, we still use the in-order scheduling model
as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer
the op. So, only when all the available instructions issued, the pending instruction
could be scheduled. That is not true for our P9 hw in fact.

This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is
picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017.

With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows:

x264_r: +6.95%
cactuBSSN_r: +6.94%
lbm_r: +4.11%
xz_r: -3.85%

And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. 

Reviewer: Nemanjai
Differential Revision: https://reviews.llvm.org/D55810

llvm-svn: 350285
2019-01-03 05:04:18 +00:00

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; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @s2v_test1(i32* nocapture readonly %int32, <4 x i32> %vec) {
; P8LE-LABEL: s2v_test1:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfiwzx f0, 0, r3
; P8LE-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; P8LE-NEXT: addi r3, r4, .LCPI0_0@toc@l
; P8LE-NEXT: lvx v4, 0, r3
; P8LE-NEXT: xxpermdi v3, f0, f0, 2
; P8LE-NEXT: vperm v2, v3, v2, v4
; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test1:
; P8BE: # %bb.0: # %entry
; P8BE: lfiwzx f0, 0, r3
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
; P8BE: xxsldwi vs0, v2, vs0, 1
; P8BE: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%0 = load i32, i32* %int32, align 4
%vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
ret <4 x i32> %vecins
}
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @s2v_test2(i32* nocapture readonly %int32, <4 x i32> %vec) {
; P8LE-LABEL: s2v_test2:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; P8LE-NEXT: lfiwzx f0, 0, r3
; P8LE-NEXT: addi r3, r4, .LCPI1_0@toc@l
; P8LE-NEXT: lvx v4, 0, r3
; P8LE-NEXT: xxpermdi v3, f0, f0, 2
; P8LE-NEXT: vperm v2, v3, v2, v4
; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test2:
; P8BE: # %bb.0: # %entry
; P8BE: addi r3, r3, 4
; P8BE: lfiwzx f0, 0, r3
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
; P8BE: xxsldwi vs0, v2, vs0, 1
; P8BE: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
%0 = load i32, i32* %arrayidx, align 4
%vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
ret <4 x i32> %vecins
}
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @s2v_test3(i32* nocapture readonly %int32, <4 x i32> %vec, i32 signext %Idx) {
; P8LE-LABEL: s2v_test3:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r5, r7, 2
; P8LE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; P8LE-NEXT: lfiwzx f0, r3, r5
; P8LE-NEXT: addi r3, r4, .LCPI2_0@toc@l
; P8LE-NEXT: lvx v4, 0, r3
; P8LE-NEXT: xxpermdi v3, f0, f0, 2
; P8LE-NEXT: vperm v2, v3, v2, v4
; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test3:
; P8BE: # %bb.0: # %entry
; P8BE: sldi r4, r7, 2
; P8BE: lfiwzx f0, r3, r4
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
; P8BE: xxsldwi vs0, v2, vs0, 1
; P8BE: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%idxprom = sext i32 %Idx to i64
%arrayidx = getelementptr inbounds i32, i32* %int32, i64 %idxprom
%0 = load i32, i32* %arrayidx, align 4
%vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
ret <4 x i32> %vecins
}
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @s2v_test4(i32* nocapture readonly %int32, <4 x i32> %vec) {
; P8LE-LABEL: s2v_test4:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; P8LE-NEXT: lfiwzx f0, 0, r3
; P8LE-NEXT: addi r3, r4, .LCPI3_0@toc@l
; P8LE-NEXT: lvx v4, 0, r3
; P8LE-NEXT: xxpermdi v3, f0, f0, 2
; P8LE-NEXT: vperm v2, v3, v2, v4
; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test4:
; P8BE: # %bb.0: # %entry
; P8BE: addi r3, r3, 4
; P8BE: lfiwzx f0, 0, r3
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
; P8BE: xxsldwi vs0, v2, vs0, 1
; P8BE: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
%0 = load i32, i32* %arrayidx, align 4
%vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
ret <4 x i32> %vecins
}
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @s2v_test5(<4 x i32> %vec, i32* nocapture readonly %ptr1) {
; P8LE-LABEL: s2v_test5:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfiwzx f0, 0, r5
; P8LE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; P8LE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; P8LE-NEXT: lvx v4, 0, r3
; P8LE-NEXT: xxpermdi v3, f0, f0, 2
; P8LE-NEXT: vperm v2, v3, v2, v4
; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test5:
; P8BE: # %bb.0: # %entry
; P8BE: lfiwzx f0, 0, r5
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
; P8BE: xxsldwi vs0, v2, vs0, 1
; P8BE: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%0 = load i32, i32* %ptr1, align 4
%vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
ret <4 x i32> %vecins
}
; Function Attrs: norecurse nounwind readonly
define <4 x float> @s2v_test_f1(float* nocapture readonly %f64, <4 x float> %vec) {
; P8LE-LABEL: s2v_test_f1:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfiwzx f0, 0, r3
; P8LE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; P8LE-NEXT: addi r3, r4, .LCPI5_0@toc@l
; P8LE-NEXT: lvx v4, 0, r3
; P8LE-NEXT: xxpermdi v3, f0, f0, 2
; P8LE-NEXT: vperm v2, v3, v2, v4
; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test_f1:
; P8BE: # %bb.0: # %entry
; P8BE: lfiwzx f0, 0, r3
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
; P8BE: xxsldwi vs0, v2, vs0, 1
; P8BE: xxsldwi v2, vs0, vs0, 3
; P8BE-NEXT: blr
entry:
%0 = load float, float* %f64, align 4
%vecins = insertelement <4 x float> %vec, float %0, i32 0
ret <4 x float> %vecins
}
; Function Attrs: norecurse nounwind readonly
define <2 x float> @s2v_test_f2(float* nocapture readonly %f64, <2 x float> %vec) {
; P9LE-LABEL: s2v_test_f2:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addi r3, r3, 4
; P9LE-DAG: xxspltw v2, v2, 2
; P9LE-DAG: lfiwzx f0, 0, r3
; P9LE-NEXT: xxpermdi v3, f0, f0, 2
; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr
; P9BE-LABEL: s2v_test_f2:
; P9BE: # %bb.0: # %entry
; P9BE: addi r3, r3, 4
; P9BE-DAG: xxspltw v2, v2, 1
; P9BE-DAG: lfiwzx f0, 0, r3
; P9BE-NEXT: xxsldwi v3, f0, f0, 1
; P9BE: vmrghw v2, v3, v2
; P9BE-NEXT: blr
; P8LE-LABEL: s2v_test_f2:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: xxspltw v2, v2, 2
; P8LE-NEXT: lfiwzx f0, 0, r3
; P8LE-NEXT: xxpermdi v3, f0, f0, 2
; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test_f2:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addi r3, r3, 4
; P8BE-NEXT: xxspltw v2, v2, 1
; P8BE-NEXT: lfiwzx f0, 0, r3
; P8BE-NEXT: xxsldwi v3, f0, f0, 1
; P8BE-NEXT: vmrghw v2, v3, v2
; P8BE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds float, float* %f64, i64 1
%0 = load float, float* %arrayidx, align 8
%vecins = insertelement <2 x float> %vec, float %0, i32 0
ret <2 x float> %vecins
}
; Function Attrs: norecurse nounwind readonly
define <2 x float> @s2v_test_f3(float* nocapture readonly %f64, <2 x float> %vec, i32 signext %Idx) {
; P9LE-LABEL: s2v_test_f3:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r7, 2
; P9LE-NEXT: lfiwzx f0, r3, r4
; P9LE-DAG: xxspltw v2, v2, 2
; P9LE-DAG: xxpermdi v3, f0, f0, 2
; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr
; P9BE-LABEL: s2v_test_f3:
; P9BE: # %bb.0: # %entry
; P9BE: sldi r4, r7, 2
; P9BE: lfiwzx f0, r3, r4
; P9BE-DAG: xxspltw v2, v2, 1
; P9BE-DAG: xxsldwi v3, f0, f0, 1
; P9BE: vmrghw v2, v3, v2
; P9BE-NEXT: blr
; P8LE-LABEL: s2v_test_f3:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r7, 2
; P8LE-NEXT: xxspltw v2, v2, 2
; P8LE-NEXT: lfiwzx f0, r3, r4
; P8LE-NEXT: xxpermdi v3, f0, f0, 2
; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test_f3:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: sldi r4, r7, 2
; P8BE-NEXT: xxspltw v2, v2, 1
; P8BE-NEXT: lfiwzx f0, r3, r4
; P8BE-NEXT: xxsldwi v3, f0, f0, 1
; P8BE-NEXT: vmrghw v2, v3, v2
; P8BE-NEXT: blr
entry:
%idxprom = sext i32 %Idx to i64
%arrayidx = getelementptr inbounds float, float* %f64, i64 %idxprom
%0 = load float, float* %arrayidx, align 8
%vecins = insertelement <2 x float> %vec, float %0, i32 0
ret <2 x float> %vecins
}
; Function Attrs: norecurse nounwind readonly
define <2 x float> @s2v_test_f4(float* nocapture readonly %f64, <2 x float> %vec) {
; P9LE-LABEL: s2v_test_f4:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addi r3, r3, 4
; P9LE-NEXT: lfiwzx f0, 0, r3
; P9LE-DAG: xxspltw v2, v2, 2
; P9LE-DAG: xxpermdi v3, f0, f0, 2
; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr
; P9BE-LABEL: s2v_test_f4:
; P9BE: # %bb.0: # %entry
; P9BE: addi r3, r3, 4
; P9BE: lfiwzx f0, 0, r3
; P9BE-DAG: xxspltw v2, v2, 1
; P9BE-DAG: xxsldwi v3, f0, f0, 1
; P9BE: vmrghw v2, v3, v2
; P9BE-NEXT: blr
; P8LE-LABEL: s2v_test_f4:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: xxspltw v2, v2, 2
; P8LE-NEXT: lfiwzx f0, 0, r3
; P8LE-NEXT: xxpermdi v3, f0, f0, 2
; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test_f4:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addi r3, r3, 4
; P8BE-NEXT: xxspltw v2, v2, 1
; P8BE-NEXT: lfiwzx f0, 0, r3
; P8BE-NEXT: xxsldwi v3, f0, f0, 1
; P8BE-NEXT: vmrghw v2, v3, v2
; P8BE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds float, float* %f64, i64 1
%0 = load float, float* %arrayidx, align 8
%vecins = insertelement <2 x float> %vec, float %0, i32 0
ret <2 x float> %vecins
}
; Function Attrs: norecurse nounwind readonly
define <2 x float> @s2v_test_f5(<2 x float> %vec, float* nocapture readonly %ptr1) {
; P9LE-LABEL: s2v_test_f5:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lfiwzx f0, 0, r5
; P9LE-NEXT: xxspltw v2, v2, 2
; P9LE-NEXT: xxpermdi v3, f0, f0, 2
; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr
; P9BE-LABEL: s2v_test_f5:
; P9BE: # %bb.0: # %entry
; P9BE: lfiwzx f0, 0, r5
; P9BE: xxspltw v2, v2, 1
; P9BE-NEXT: xxsldwi v3, f0, f0, 1
; P9BE: vmrghw v2, v3, v2
; P9BE-NEXT: blr
; P8LE-LABEL: s2v_test_f5:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfiwzx f0, 0, r5
; P8LE-NEXT: xxspltw v2, v2, 2
; P8LE-NEXT: xxpermdi v3, f0, f0, 2
; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test_f5:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfiwzx f0, 0, r5
; P8BE-NEXT: xxspltw v2, v2, 1
; P8BE-NEXT: xxsldwi v3, f0, f0, 1
; P8BE-NEXT: vmrghw v2, v3, v2
; P8BE-NEXT: blr
entry:
%0 = load float, float* %ptr1, align 8
%vecins = insertelement <2 x float> %vec, float %0, i32 0
ret <2 x float> %vecins
}
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