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https://github.com/RPCS3/llvm-mirror.git
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1d5f4c66da
This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Assembler/disassembler support for new instructions. - CodeGen for new instructions, including new LLVM intrinsics. - Scheduler description for the new processor. - Detection of arch13 as host processor. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365932
144 lines
2.9 KiB
LLVM
144 lines
2.9 KiB
LLVM
; Test LOCHI and LOCGHI.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s
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;
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; Run the test again to make sure it still works the same even
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; in the presence of the select instructions.
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 -verify-machineinstrs | FileCheck %s
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define i32 @f1(i32 %x) {
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; CHECK-LABEL: f1:
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; CHECK: chi %r2, 0
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; CHECK: lhi %r2, 0
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; CHECK: lochilh %r2, 42
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; CHECK: br %r14
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%cond = icmp ne i32 %x, 0
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%res = select i1 %cond, i32 42, i32 0
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ret i32 %res
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}
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define i32 @f2(i32 %x, i32 %y) {
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; CHECK-LABEL: f2:
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; CHECK: chi %r2, 0
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; CHECK: lochilh %r3, 42
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; CHECK: br %r14
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%cond = icmp ne i32 %x, 0
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%res = select i1 %cond, i32 42, i32 %y
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ret i32 %res
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}
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define i32 @f3(i32 %x, i32 %y) {
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; CHECK-LABEL: f3:
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; CHECK: chi %r2, 0
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; CHECK: lochie %r3, 42
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; CHECK: br %r14
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%cond = icmp ne i32 %x, 0
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%res = select i1 %cond, i32 %y, i32 42
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ret i32 %res
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}
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define i64 @f4(i64 %x) {
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; CHECK-LABEL: f4:
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; CHECK: cghi %r2, 0
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; CHECK: lghi %r2, 0
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; CHECK: locghilh %r2, 42
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; CHECK: br %r14
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%cond = icmp ne i64 %x, 0
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%res = select i1 %cond, i64 42, i64 0
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ret i64 %res
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}
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define i64 @f5(i64 %x, i64 %y) {
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; CHECK-LABEL: f5:
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; CHECK: cghi %r2, 0
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; CHECK: locghilh %r3, 42
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; CHECK: br %r14
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%cond = icmp ne i64 %x, 0
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%res = select i1 %cond, i64 42, i64 %y
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ret i64 %res
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}
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define i64 @f6(i64 %x, i64 %y) {
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; CHECK-LABEL: f6:
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; CHECK: cghi %r2, 0
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; CHECK: locghie %r3, 42
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; CHECK: br %r14
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%cond = icmp ne i64 %x, 0
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%res = select i1 %cond, i64 %y, i64 42
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ret i64 %res
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}
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; Check that we also get LOCHI as a result of early if-conversion.
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define i32 @f7(i32 %x, i32 %y) {
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; CHECK-LABEL: f7:
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; CHECK: chi %r2, 0
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; CHECK: lochie %r3, 42
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; CHECK: br %r14
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entry:
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%cond = icmp ne i32 %x, 0
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br i1 %cond, label %if.then, label %return
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if.then:
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br label %return
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return:
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%res = phi i32 [ %y, %if.then ], [ 42, %entry ]
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ret i32 %res
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}
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; ... and the same for LOCGHI.
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define i64 @f8(i64 %x, i64 %y) {
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; CHECK-LABEL: f8:
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; CHECK: cghi %r2, 0
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; CHECK: locghie %r3, 42
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; CHECK: br %r14
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entry:
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%cond = icmp ne i64 %x, 0
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br i1 %cond, label %if.then, label %return
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if.then:
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br label %return
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return:
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%res = phi i64 [ %y, %if.then ], [ 42, %entry ]
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ret i64 %res
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}
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; Check that inverting the condition works as well.
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define i32 @f9(i32 %x, i32 %y) {
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; CHECK-LABEL: f9:
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; CHECK: chi %r2, 0
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; CHECK: lochilh %r3, 42
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; CHECK: br %r14
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entry:
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%cond = icmp ne i32 %x, 0
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br i1 %cond, label %if.then, label %return
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if.then:
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br label %return
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return:
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%res = phi i32 [ 42, %if.then ], [ %y, %entry ]
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ret i32 %res
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}
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; ... and the same for LOCGHI.
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define i64 @f10(i64 %x, i64 %y) {
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; CHECK-LABEL: f10:
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; CHECK: cghi %r2, 0
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; CHECK: locghilh %r3, 42
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; CHECK: br %r14
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entry:
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%cond = icmp ne i64 %x, 0
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br i1 %cond, label %if.then, label %return
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if.then:
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br label %return
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return:
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%res = phi i64 [ 42, %if.then ], [ %y, %entry ]
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ret i64 %res
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}
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