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llvm-mirror/test/CodeGen/SystemZ/debuginstr-02.mir
Matt Arsenault 23c462a8b5 Rename ExpandISelPseudo->FinalizeISel, delay register reservation
This allows targets to make more decisions about reserved registers
after isel. For example, now it should be certain there are calls or
stack objects in the frame or not, which could have been introduced by
legalization.

Patch by Matthias Braun

llvm-svn: 363757
2019-06-19 00:25:39 +00:00

94 lines
3.4 KiB
YAML

# Check that the backend can handle consecutive select instructions also in
# the presence of DEBUG_VALUE machine instructions.
#
# RUN: llc %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \
# RUN: -start-before=finalize-isel -o - 2>&1 | FileCheck %s
#
# CHECK-LABEL: %bb.1:
# CHECK: ldr
# CHECK-NEXT: ldr
# CHECK-NEXT: ldr
--- |
; ModuleID = 'tc.ll'
source_filename = "tc.ll"
target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
define float @fun(i1 %cmp, float %arg0, float %arg1, float %arg2, float %arg3, float %arg4) #0 {
%fs0 = select i1 %cmp, float %arg0, float %arg1
; Keep the dbg metadata live by referencing it in the IR.
call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !DIExpression()), !dbg !9
%fs1 = select i1 %cmp, float %arg2, float %arg3
call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !DIExpression()), !dbg !9
%fs2 = select i1 %cmp, float %arg0, float %arg3
%s0 = fadd float %fs0, %fs1
%s1 = fadd float %s0, %fs2
ret float %s1
}
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
attributes #0 = { "target-cpu"="z13" }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "llvm", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
!1 = !DIFile(filename: "test.ll", directory: "/tmp")
!2 = !{}
!3 = !{i32 2, !"Dwarf Version", i32 4}
!4 = !{i32 2, !"Debug Info Version", i32 3}
!5 = distinct !DISubprogram(name: "test_dbg_value", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !2)
!6 = !DISubroutineType(types: !2)
!7 = !DILocalVariable(name: "in", arg: 1, scope: !5, file: !1, line: 1, type: !8)
!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
!9 = !DILocation(line: 1, column: 1, scope: !5)
...
---
name: fun
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: gr32bit }
- { id: 1, class: fp32bit }
- { id: 2, class: fp32bit }
- { id: 3, class: fp32bit }
- { id: 4, class: fp32bit }
- { id: 5, class: fp32bit }
- { id: 6, class: fp32bit }
- { id: 7, class: fp32bit }
- { id: 8, class: fp32bit }
- { id: 9, class: fp32bit }
liveins:
- { reg: '$r2l', virtual-reg: '%0' }
- { reg: '$f0s', virtual-reg: '%1' }
- { reg: '$f2s', virtual-reg: '%2' }
- { reg: '$f4s', virtual-reg: '%3' }
- { reg: '$f6s', virtual-reg: '%4' }
frameInfo:
maxAlignment: 8
fixedStack:
- { id: 0, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.0 (%ir-block.0):
liveins: $r2l, $f0s, $f2s, $f4s, $f6s
%4:fp32bit = COPY $f6s
%3:fp32bit = COPY $f4s
%2:fp32bit = COPY $f2s
%1:fp32bit = COPY $f0s
%0:gr32bit = COPY $r2l
TMLMux %0, 1, implicit-def $cc
%5:fp32bit = SelectVR32 %1, %2, 15, 7, implicit $cc
DBG_VALUE %5, $noreg, !7, !DIExpression(), debug-location !9
%6:fp32bit = SelectVR32 %3, %4, 15, 7, implicit $cc
DBG_VALUE %6, $noreg, !7, !DIExpression(), debug-location !9
%7:fp32bit = SelectVR32 %1, %4, 15, 7, implicit $cc
%8:fp32bit = AEBR %5, killed %6, implicit-def dead $cc, implicit $fpc
%9:fp32bit = AEBR %8, killed %7, implicit-def dead $cc, implicit $fpc
$f0s = COPY %9
Return implicit $f0s
...