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0ea6a75196
Describe parameter's value loaded by MIPS ADDiu instruction. When parameter's value is loaded into a register by mips ADDiu/DADDiu instruction, it could be described correctly and emitted as DW_AT_GNU_call_site_value. Patch by Nikola Tesic Differential revision: https://reviews.llvm.org/D78108
198 lines
7.9 KiB
C++
198 lines
7.9 KiB
C++
//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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// FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
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// order for MipsLongBranch pass to work correctly when the code has inline
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// assembly. The returned value doesn't have to be the asm instruction's exact
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// size in bytes; MipsLongBranch only expects it to be the correct upper bound.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
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#define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include <cstdint>
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#define GET_INSTRINFO_HEADER
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#include "MipsGenInstrInfo.inc"
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namespace llvm {
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class MachineInstr;
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class MachineOperand;
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class MipsSubtarget;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class MipsInstrInfo : public MipsGenInstrInfo {
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virtual void anchor();
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protected:
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const MipsSubtarget &Subtarget;
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unsigned UncondBrOpc;
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public:
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enum BranchType {
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BT_None, // Couldn't analyze branch.
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BT_NoBranch, // No branches found.
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BT_Uncond, // One unconditional branch.
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BT_Cond, // One conditional branch.
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BT_CondUncond, // A conditional branch followed by an unconditional branch.
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BT_Indirect // One indirct branch.
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};
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explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
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static const MipsInstrInfo *create(MipsSubtarget &STI);
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/// Branch Analysis
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify,
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SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
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/// Determine the opcode of a non-delay slot form for a branch if one exists.
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unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;
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/// Determine if the branch target is in range.
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bool isBranchOffsetInRange(unsigned BranchOpc,
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int64_t BrOffset) const override;
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/// Predicate to determine if an instruction can go in a forbidden slot.
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bool SafeInForbiddenSlot(const MachineInstr &MI) const;
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/// Predicate to determine if an instruction has a forbidden slot.
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bool HasForbiddenSlot(const MachineInstr &MI) const;
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/// Insert nop instruction when hazard condition is found
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
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virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
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virtual bool isBranchWithImm(unsigned Opc) const {
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return false;
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}
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/// Return the number of bytes of code the specified instruction may be.
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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Register SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override {
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storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
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}
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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Register DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override {
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loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
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}
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virtual void storeRegToStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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Register SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const = 0;
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virtual void loadRegFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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Register DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const = 0;
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virtual void adjustStackPtr(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const = 0;
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/// Create an instruction which has the same operands and memory operands
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/// as MI but has a new opcode.
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MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
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MachineBasicBlock::iterator I) const;
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bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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/// Perform target specific instruction verification.
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bool verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const override;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
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Register Reg) const override;
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Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
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Register Reg) const override;
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protected:
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bool isZeroImm(const MachineOperand &op) const;
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MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
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MachineMemOperand::Flags Flags) const;
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private:
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virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
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void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
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MachineBasicBlock *&BB,
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SmallVectorImpl<MachineOperand> &Cond) const;
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void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
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};
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/// Create MipsInstrInfo objects.
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const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
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const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
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