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The current pattern matching for zext results in the following code snippet being produced, w1 = w0 r1 <<= 32 r1 >>= 32 Because BPF implementations require zero extension on 32bit loads this both adds a few extra unneeded instructions but also makes it a bit harder for the verifier to track the r1 register bounds. For example in this verifier trace we see at the end of the snippet R2 offset is unknown. However, if we track this correctly we see w1 should have the same bounds as r8. R8 smax is less than U32 max value so a zero extend load should keep the same value. Adding a max value of 800 (R8=inv(id=0,smax_value=800)) to an off=0, as seen in R7 should create a max offset of 800. However at the end of the snippet we note the R2 max offset is 0xffffFFFF. R0=inv(id=0,smax_value=800) R1_w=inv(id=0,umax_value=2147483647,var_off=(0x0; 0x7fffffff)) R6=ctx(id=0,off=0,imm=0) R7=map_value(id=0,off=0,ks=4,vs=1600,imm=0) R8_w=inv(id=0,smax_value=800,umax_value=4294967295,var_off=(0x0; 0xffffffff)) R9=inv800 R10=fp0 fp-8=mmmm???? 58: (1c) w9 -= w8 59: (bc) w1 = w8 60: (67) r1 <<= 32 61: (77) r1 >>= 32 62: (bf) r2 = r7 63: (0f) r2 += r1 64: (bf) r1 = r6 65: (bc) w3 = w9 66: (b7) r4 = 0 67: (85) call bpf_get_stack#67 R0=inv(id=0,smax_value=800) R1_w=ctx(id=0,off=0,imm=0) R2_w=map_value(id=0,off=0,ks=4,vs=1600,umax_value=4294967295,var_off=(0x0; 0xffffffff)) R3_w=inv(id=0,umax_value=800,var_off=(0x0; 0x3ff)) R4_w=inv0 R6=ctx(id=0,off=0,imm=0) R7=map_value(id=0,off=0,ks=4,vs=1600,imm=0) R8_w=inv(id=0,smax_value=800,umax_value=4294967295,var_off=(0x0; 0xffffffff)) R9_w=inv(id=0,umax_value=800,var_off=(0x0; 0x3ff)) R10=fp0 fp-8=mmmm???? After this patch R1 bounds are not smashed by the <<=32 >>=32 shift and we get correct bounds on R2 umax_value=800. Further it reduces 3 insns to 1. Signed-off-by: John Fastabend <john.fastabend@gmail.com> Differential Revision: https://reviews.llvm.org/D73985
35 lines
1.0 KiB
LLVM
35 lines
1.0 KiB
LLVM
; RUN: llc -O2 -march=bpfel -mcpu=v2 -mattr=+alu32 < %s | FileCheck %s
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;
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; For the below test case, 'b' in 'ret == b' needs SLL/SLR.
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; 'ret' in 'ret == b' does not need SLL/SLR as all 'ret' values
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; are assigned through 'w<reg> = <value>' alu32 operations.
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;
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; extern int helper(int);
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; int test(int a, int b, int c, int d) {
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; int ret;
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; if (a < b)
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; ret = (c < d) ? -1 : 0;
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; else
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; ret = (c < a) ? 1 : 2;
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; return helper(ret == b);
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; }
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define dso_local i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr {
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entry:
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%cmp = icmp slt i32 %a, %b
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%cmp1 = icmp slt i32 %c, %d
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%cond = sext i1 %cmp1 to i32
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%cmp2 = icmp slt i32 %c, %a
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%cond3 = select i1 %cmp2, i32 1, i32 2
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%ret.0 = select i1 %cmp, i32 %cond, i32 %cond3
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%cmp4 = icmp eq i32 %ret.0, %b
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%conv = zext i1 %cmp4 to i32
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%call = tail call i32 @helper(i32 %conv)
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ret i32 %call
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}
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; CHECK: r{{[0-9]+}} = w{{[0-9]+}}
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; CHECK-NOT: r{{[0-9]+}} >>= 32
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; CHECK: if r{{[0-9]+}} == r{{[0-9]+}} goto
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declare dso_local i32 @helper(i32) local_unnamed_addr
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