Chris Lattner d188e03011 Take register pressure into account when we have to decide whether to ... evaluate the LHS or the RHS of an operation first. This causes good things to happen. For example, instead of compiling a loop to this: .LBBstrength_result7_1: # loopentry movl 16(%esp), %edi movl (%edi), %edi ;;; LOAD movl (%ecx), %ebx movl $2, (%eax,%ebx,4) movl (%edx), %ebx movl %esi, %ebp addl $21, %ebp addl $42, %esi cmpl $0, %edi ;;; USE cmovne %esi, %ebp cmpl %ebp, %ebx movl %ebp, %esi jg .LBBstrength_result7_1 We now compile it to this: .LBBstrength_result7_1: # loopentry movl %edi, %ebx addl $42, %ebx addl $21, %edi movl (%ecx), %ebp ;; LOAD cmpl $0, %ebp ;; USE cmovne %ebx, %edi movl (%edx), %ebx movl $2, (%eax,%ebx,4) movl (%esi), %ebx cmpl %edi, %ebx jg .LBBstrength_result7_1 Which reduces register pressure enough (in this case) to avoid spilling in the loop. As another example, consider the CodeGen/X86/regpressure.ll testcase. We used to generate this code for both cases: regpressure1: subl $32, %esp movl %esi, 12(%esp) movl %edi, 8(%esp) movl %ebx, 4(%esp) movl %ebp, (%esp) movl 36(%esp), %ecx movl (%ecx), %eax movl 4(%ecx), %edx movl %edx, 24(%esp) movl 8(%ecx), %edx movl %edx, 16(%esp) movl 12(%ecx), %edx movl 16(%ecx), %esi movl 20(%ecx), %edi movl 24(%ecx), %ebx movl %ebx, 28(%esp) movl 28(%ecx), %ebx movl 32(%ecx), %ebp movl %ebp, 20(%esp) movl 36(%ecx), %ecx imull 24(%esp), %eax imull 16(%esp), %eax imull %edx, %eax imull %esi, %eax imull %edi, %eax imull 28(%esp), %eax imull %ebx, %eax imull 20(%esp), %eax imull %ecx, %eax movl (%esp), %ebp movl 4(%esp), %ebx movl 8(%esp), %edi movl 12(%esp), %esi addl $32, %esp ret This code is basically trying to do all of the loads first, then execute all of the multiplies. Because we run out of registers, lots of spill code happens. We now generate this code for both cases: regpressure1: movl 4(%esp), %ecx movl (%ecx), %eax movl 4(%ecx), %edx imull %edx, %eax movl 8(%ecx), %edx imull %edx, %eax movl 12(%ecx), %edx imull %edx, %eax movl 16(%ecx), %edx imull %edx, %eax movl 20(%ecx), %edx imull %edx, %eax movl 24(%ecx), %edx imull %edx, %eax movl 28(%ecx), %edx imull %edx, %eax movl 32(%ecx), %edx imull %edx, %eax movl 36(%ecx), %ecx imull %ecx, %eax ret which is much nicer (when we fold loads into the muls it will be even better). The old instruction selector used to produce the good code for regpressure1 but not for regpressure2, as it depended on the order of operations in the LLVM code. llvm-svn: 19449		2005-01-11 03:11:44 +00:00
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CBackend	Fix CBE code so that it compiles with VC++.	2005-01-06 04:21:49 +00:00
PowerPC	This hunk:	2005-01-02 23:07:31 +00:00
Skeleton	ignore generated files	2004-11-21 00:01:54 +00:00
SparcV8	Substantially improve the code generated by non-folded setcc instructions.	2005-01-01 16:06:57 +00:00
SparcV9	Chris is a pain ;) Removing reassociate.	2004-12-16 23:16:16 +00:00
X86	Take register pressure into account when we have to decide whether to	2005-01-11 03:11:44 +00:00
Makefile	Add SparcV8 target back into the build	2004-12-10 04:54:21 +00:00
MRegisterInfo.cpp	Move destructor out of line to avoid vtable emission in every file that includes the header. Thanks to sabre.	2004-10-27 06:00:53 +00:00
Target.td	Add some bits that can be set for instructions.	2005-01-02 02:27:48 +00:00
TargetData.cpp	Initial support for packed types, contributed by Morten Ofstad	2004-12-01 17:14:28 +00:00
TargetFrameInfo.cpp	Remove dead methods	2004-08-12 18:37:15 +00:00
TargetInstrInfo.cpp	ConstantTypeMustBeLoaded has been incorporated into SparcV9PreSelection, its	2004-07-27 21:43:38 +00:00
TargetLowering.cpp	First draft of new Target interface	2005-01-07 07:44:53 +00:00
TargetMachine.cpp	Changes For Bug 352	2004-09-01 22:55:40 +00:00
TargetMachineRegistry.cpp	Implement TargetRegistrationListener	2004-07-11 06:03:21 +00:00
TargetSchedInfo.cpp	Remove dead assert	2004-10-25 19:04:01 +00:00