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https://github.com/RPCS3/llvm-mirror.git
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f56d44dbb2
Summary: * Similiar to the ARM backend yse the peephole optimizer to generate more conditional ALU operations; * Add predicated type with default always true to RR instructions in LanaiInstrInfo.td; * Move LanaiSetflagAluCombiner into optimizeCompare; * The ASM parser can currently only handle explicitly specified CC, so specify ".t" (true) where needed in the ASM test; * Remove unused MachineOperand flags; Reviewers: eliben Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D22072 llvm-svn: 274807
36 lines
1.1 KiB
CMake
36 lines
1.1 KiB
CMake
set(LLVM_TARGET_DEFINITIONS Lanai.td)
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tablegen(LLVM LanaiGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM LanaiGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM LanaiGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM LanaiGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM LanaiGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM LanaiGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM LanaiGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM LanaiGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM LanaiGenSubtargetInfo.inc -gen-subtarget)
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add_public_tablegen_target(LanaiCommonTableGen)
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add_llvm_target(LanaiCodeGen
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LanaiAsmPrinter.cpp
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LanaiDelaySlotFiller.cpp
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LanaiFrameLowering.cpp
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LanaiInstrInfo.cpp
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LanaiISelDAGToDAG.cpp
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LanaiISelLowering.cpp
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LanaiMachineFunctionInfo.cpp
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LanaiMCInstLower.cpp
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LanaiMemAluCombiner.cpp
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LanaiRegisterInfo.cpp
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LanaiSelectionDAGInfo.cpp
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LanaiSubtarget.cpp
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LanaiTargetMachine.cpp
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LanaiTargetObjectFile.cpp
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)
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add_subdirectory(AsmParser)
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add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(InstPrinter)
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add_subdirectory(Disassembler)
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