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c2d816d704
TargetSubtargetInfo::overrideSchedPolicy takes two MachineInstr* arguments (begin and end) that invite implicit conversions from MachineInstrBundleIterator. One option would be to change their type to an iterator, but since they don't seem to have been used since the API was added in 2010, I'm deleting the dead code. llvm-svn: 274304
318 lines
10 KiB
C++
318 lines
10 KiB
C++
//===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PowerPC specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
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#define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
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#include "PPCFrameLowering.h"
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#include "PPCISelLowering.h"
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#include "PPCInstrInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "PPCGenSubtargetInfo.inc"
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// GCC #defines PPC on Linux but we use it as our namespace name
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#undef PPC
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namespace llvm {
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class StringRef;
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namespace PPC {
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// -m directive values.
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enum {
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DIR_NONE,
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DIR_32,
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DIR_440,
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DIR_601,
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DIR_602,
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DIR_603,
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DIR_7400,
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DIR_750,
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DIR_970,
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DIR_A2,
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DIR_E500mc,
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DIR_E5500,
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DIR_PWR3,
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DIR_PWR4,
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DIR_PWR5,
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DIR_PWR5X,
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DIR_PWR6,
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DIR_PWR6X,
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DIR_PWR7,
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DIR_PWR8,
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DIR_PWR9,
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DIR_64
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};
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}
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class GlobalValue;
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class TargetMachine;
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class PPCSubtarget : public PPCGenSubtargetInfo {
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public:
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enum POPCNTDKind {
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POPCNTD_Unavailable,
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POPCNTD_Slow,
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POPCNTD_Fast
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};
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protected:
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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unsigned StackAlignment;
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/// Selected instruction itineraries (one entry per itinerary class.)
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InstrItineraryData InstrItins;
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/// Which cpu directive was used.
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unsigned DarwinDirective;
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/// Used by the ISel to turn in optimizations for POWER4-derived architectures
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bool HasMFOCRF;
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bool Has64BitSupport;
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bool Use64BitRegs;
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bool UseCRBits;
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bool UseSoftFloat;
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bool IsPPC64;
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bool HasAltivec;
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bool HasSPE;
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bool HasQPX;
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bool HasVSX;
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bool HasP8Vector;
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bool HasP8Altivec;
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bool HasP8Crypto;
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bool HasP9Vector;
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bool HasP9Altivec;
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bool HasFCPSGN;
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bool HasFSQRT;
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bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
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bool HasRecipPrec;
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bool HasSTFIWX;
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bool HasLFIWAX;
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bool HasFPRND;
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bool HasFPCVT;
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bool HasISEL;
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bool HasBPERMD;
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bool HasExtDiv;
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bool HasCMPB;
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bool HasLDBRX;
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bool IsBookE;
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bool HasOnlyMSYNC;
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bool IsE500;
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bool IsPPC4xx;
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bool IsPPC6xx;
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bool FeatureMFTB;
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bool DeprecatedDST;
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bool HasLazyResolverStubs;
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bool IsLittleEndian;
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bool HasICBT;
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bool HasInvariantFunctionDescriptors;
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bool HasPartwordAtomics;
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bool HasDirectMove;
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bool HasHTM;
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bool HasFusion;
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bool HasFloat128;
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bool IsISA3_0;
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POPCNTDKind HasPOPCNTD;
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/// When targeting QPX running a stock PPC64 Linux kernel where the stack
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/// alignment has not been changed, we need to keep the 16-byte alignment
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/// of the stack.
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bool IsQPXStackUnaligned;
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const PPCTargetMachine &TM;
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PPCFrameLowering FrameLowering;
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PPCInstrInfo InstrInfo;
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PPCTargetLowering TLInfo;
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SelectionDAGTargetInfo TSInfo;
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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///
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PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
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const PPCTargetMachine &TM);
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// function for this subtarget.
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unsigned getStackAlignment() const { return StackAlignment; }
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/// getDarwinDirective - Returns the -m directive specified for the cpu.
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///
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unsigned getDarwinDirective() const { return DarwinDirective; }
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/// getInstrItins - Return the instruction itineraries based on subtarget
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/// selection.
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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const PPCFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const PPCTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const PPCRegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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const PPCTargetMachine &getTargetMachine() const { return TM; }
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/// initializeSubtargetDependencies - Initializes using a CPU and feature string
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/// so that we can use initializer lists for subtarget initialization.
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PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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private:
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void initializeEnvironment();
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void initSubtargetFeatures(StringRef CPU, StringRef FS);
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public:
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/// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
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///
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bool isPPC64() const;
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/// has64BitSupport - Return true if the selected CPU supports 64-bit
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/// instructions, regardless of whether we are in 32-bit or 64-bit mode.
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bool has64BitSupport() const { return Has64BitSupport; }
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// useSoftFloat - Return true if soft-float option is turned on.
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bool useSoftFloat() const { return UseSoftFloat; }
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/// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
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/// registers in 32-bit mode when possible. This can only true if
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/// has64BitSupport() returns true.
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bool use64BitRegs() const { return Use64BitRegs; }
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/// useCRBits - Return true if we should store and manipulate i1 values in
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/// the individual condition register bits.
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bool useCRBits() const { return UseCRBits; }
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/// hasLazyResolverStub - Return true if accesses to the specified global have
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/// to go through a dyld lazy resolution stub. This means that an extra load
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/// is required to get the address of the global.
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bool hasLazyResolverStub(const GlobalValue *GV) const;
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// isLittleEndian - True if generating little-endian code
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bool isLittleEndian() const { return IsLittleEndian; }
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// Specific obvious features.
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bool hasFCPSGN() const { return HasFCPSGN; }
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bool hasFSQRT() const { return HasFSQRT; }
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bool hasFRE() const { return HasFRE; }
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bool hasFRES() const { return HasFRES; }
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bool hasFRSQRTE() const { return HasFRSQRTE; }
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bool hasFRSQRTES() const { return HasFRSQRTES; }
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bool hasRecipPrec() const { return HasRecipPrec; }
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bool hasSTFIWX() const { return HasSTFIWX; }
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bool hasLFIWAX() const { return HasLFIWAX; }
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bool hasFPRND() const { return HasFPRND; }
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bool hasFPCVT() const { return HasFPCVT; }
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bool hasAltivec() const { return HasAltivec; }
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bool hasSPE() const { return HasSPE; }
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bool hasQPX() const { return HasQPX; }
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bool hasVSX() const { return HasVSX; }
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bool hasP8Vector() const { return HasP8Vector; }
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bool hasP8Altivec() const { return HasP8Altivec; }
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bool hasP8Crypto() const { return HasP8Crypto; }
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bool hasP9Vector() const { return HasP9Vector; }
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bool hasP9Altivec() const { return HasP9Altivec; }
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bool hasMFOCRF() const { return HasMFOCRF; }
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bool hasISEL() const { return HasISEL; }
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bool hasBPERMD() const { return HasBPERMD; }
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bool hasExtDiv() const { return HasExtDiv; }
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bool hasCMPB() const { return HasCMPB; }
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bool hasLDBRX() const { return HasLDBRX; }
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bool isBookE() const { return IsBookE; }
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bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
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bool isPPC4xx() const { return IsPPC4xx; }
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bool isPPC6xx() const { return IsPPC6xx; }
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bool isE500() const { return IsE500; }
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bool isFeatureMFTB() const { return FeatureMFTB; }
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bool isDeprecatedDST() const { return DeprecatedDST; }
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bool hasICBT() const { return HasICBT; }
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bool hasInvariantFunctionDescriptors() const {
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return HasInvariantFunctionDescriptors;
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}
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bool hasPartwordAtomics() const { return HasPartwordAtomics; }
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bool hasDirectMove() const { return HasDirectMove; }
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bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
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unsigned getPlatformStackAlignment() const {
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if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
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return 32;
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return 16;
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}
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bool hasHTM() const { return HasHTM; }
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bool hasFusion() const { return HasFusion; }
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bool hasFloat128() const { return HasFloat128; }
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bool isISA3_0() const { return IsISA3_0; }
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POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
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const Triple &getTargetTriple() const { return TargetTriple; }
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/// isDarwin - True if this is any darwin platform.
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bool isDarwin() const { return TargetTriple.isMacOSX(); }
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/// isBGQ - True if this is a BG/Q platform.
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bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
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bool isSVR4ABI() const { return !isDarwinABI(); }
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bool isELFv2ABI() const;
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bool enableEarlyIfConversion() const override { return hasISEL(); }
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// Scheduling customization.
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bool enableMachineScheduler() const override;
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// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
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bool enablePostRAScheduler() const override;
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AntiDepBreakMode getAntiDepBreakMode() const override;
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void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
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void overrideSchedPolicy(MachineSchedPolicy &Policy,
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unsigned NumRegionInstrs) const override;
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bool useAA() const override;
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bool enableSubRegLiveness() const override;
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/// classifyGlobalReference - Classify a global variable reference for the
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/// current subtarget accourding to how we should reference it.
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unsigned char classifyGlobalReference(const GlobalValue *GV) const;
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};
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} // End llvm namespace
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#endif
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