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Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 llvm-svn: 274856
161 lines
5.7 KiB
TableGen
161 lines
5.7 KiB
TableGen
//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// SPARC Subtarget features.
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//
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def FeatureV9
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: SubtargetFeature<"v9", "IsV9", "true", "Enable SPARC-V9 instructions">;
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def FeatureV8Deprecated
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: SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true",
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"Enable deprecated V8 instructions in V9 mode">;
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def FeatureVIS
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: SubtargetFeature<"vis", "IsVIS", "true",
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"Enable UltraSPARC Visual Instruction Set extensions">;
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def FeatureVIS2
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: SubtargetFeature<"vis2", "IsVIS2", "true",
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"Enable Visual Instruction Set extensions II">;
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def FeatureVIS3
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: SubtargetFeature<"vis3", "IsVIS3", "true",
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"Enable Visual Instruction Set extensions III">;
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def FeatureLeon
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: SubtargetFeature<"leon", "IsLeon", "true", "Enable LEON extensions">;
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def FeatureHardQuad
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: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
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"Enable quad-word floating point instructions">;
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def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
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"Use the popc (population count) instruction">;
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def FeatureSoftFloat
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: SubtargetFeature<"soft-float", "UseSoftFloat", "true",
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"Use software emulation for floating point">;
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//==== Features added predmoninantly for LEON subtarget support
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include "LeonFeatures.td"
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "SparcRegisterInfo.td"
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include "SparcCallingConv.td"
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include "SparcSchedule.td"
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include "SparcInstrInfo.td"
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def SparcInstrInfo : InstrInfo;
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def SparcAsmParser : AsmParser { bit ShouldEmitMatchRegisterName = 0; }
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//===----------------------------------------------------------------------===//
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// SPARC processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"v7", []>;
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def : Proc<"v8", []>;
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def : Proc<"supersparc", []>;
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def : Proc<"sparclite", []>;
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def : Proc<"f934", []>;
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def : Proc<"hypersparc", []>;
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def : Proc<"sparclite86x", []>;
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def : Proc<"sparclet", []>;
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def : Proc<"tsc701", []>;
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def : Proc<"myriad2", []>;
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def : Proc<"myriad2.1", []>;
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def : Proc<"myriad2.2", []>;
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def : Proc<"v9", [ FeatureV9 ]>;
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def : Proc<"ultrasparc", [ FeatureV9, FeatureV8Deprecated, FeatureVIS ]>;
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def : Proc<"ultrasparc3",
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[ FeatureV9, FeatureV8Deprecated, FeatureVIS, FeatureVIS2 ]>;
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def : Proc<"niagara",
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[ FeatureV9, FeatureV8Deprecated, FeatureVIS, FeatureVIS2 ]>;
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def : Proc<"niagara2", [
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FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2
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]>;
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def : Proc<"niagara3", [
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FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2
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]>;
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def : Proc<"niagara4", [
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FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2, FeatureVIS3
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]>;
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// LEON 2 FT generic
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def : Processor<"leon2", LEON2Itineraries, [ FeatureLeon ]>;
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// LEON 2 FT (AT697E)
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// AT697E: Provides full coverage of AT697E - covers all the erratum fixes for
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// LEON2 AT697E
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def : Processor<"at697e", LEON2Itineraries, [
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FeatureLeon, ReplaceSDIV, FixCALL, IgnoreZeroFlag, InsertNOPDoublePrecision
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]>;
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// LEON 2 FT (AT697F)
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// AT697F: Provides full coverage of AT697F - covers all the erratum fixes for
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// LEON2 AT697F
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def : Processor<"at697f", LEON2Itineraries,
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[ FeatureLeon, InsertNOPDoublePrecision ]>;
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// LEON 3 FT generic
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def : Processor<"leon3", LEON3Itineraries, [ FeatureLeon, UMACSMACSupport ]>;
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// LEON 3 FT (UT699). Provides features for the UT699 processor
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// - covers all the erratum fixes for LEON3, but does not support the CASA
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// instruction.
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def : Processor<"ut699", LEON3Itineraries, [
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FeatureLeon, FixFSMULD, ReplaceFMULS, PreventRoundChange,
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FixAllFDIVSQRT, InsertNOPLoad, FlushCacheLineSWAP, InsertNOPsLoadStore
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]>;
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// LEON3 FT (GR712RC). Provides features for the GR712RC processor.
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// - covers all the erratum fixed for LEON3 and support for the CASA
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// instruction.
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def : Processor<"gr712rc", LEON3Itineraries,
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[ FeatureLeon, LeonCASA ]>;
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// LEON 4 FT generic
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def : Processor<"leon4", LEON4Itineraries,
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[ FeatureLeon, LeonCASA ]>;
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// GR740: Provides full coverage of GR740 - covers all the erratum fixes for
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// LEON3 + support to CASA + LEON 4 instruction timings
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def : Processor<"gr740", LEON4Itineraries,
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[ FeatureLeon, LeonCASA ]> {}
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def SparcAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int PassSubtarget = 1;
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int Variant = 0;
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}
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def Sparc : Target {
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// Pull in Instruction Info:
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let InstructionSet = SparcInstrInfo;
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let AssemblyParsers = [ SparcAsmParser ];
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let AssemblyWriters = [ SparcAsmWriter ];
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}
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