Sanjay Patel d1a8bb697a [Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics ... The vector reduction intrinsics started life as experimental ops, so backend support was lacking. As part of promoting them to 1st-class intrinsics, however, codegen support was added/improved: D58015 D90247 So I think it is safe to now remove this complication from IR. Note that we still have an IR-level codegen expansion pass for these as discussed in D95690. Removing that is another step in simplifying the logic. Also note that x86 was already unconditionally forming reductions in IR, so there should be no difference for x86. I spot checked a couple of the tests here by running them through opt+llc and did not see any asm diffs. If we do find functional differences for other targets, it should be possible to (at least temporarily) restore the shuffle IR with the ExpandReductions IR pass. Differential Revision: https://reviews.llvm.org/D96552		2021-02-12 08:13:50 -05:00
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llvm	[Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics	2021-02-12 08:13:50 -05:00
llvm-c	[llvm-c] Move LLVMX86_AMXTypeKind & LLVMPoisonValueValueKind to the bottom to avoid value changes compared with LLVM<=11	2021-01-27 16:28:04 -08:00