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46e43049cf
Implement shouldCoalesce() to help regalloc avoid running out of GR128 registers. If a COPY involving a subreg of a GR128 is coalesced, the live range of the GR128 virtual register will be extended. If this happens where there are enough phys-reg clobbers present, regalloc will run out of registers (if there is not a single GR128 allocatable register available). This patch tries to allow coalescing only when it can prove that this will be safe by checking the (local) interval in question. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D37899 https://bugs.llvm.org/show_bug.cgi?id=34610 llvm-svn: 314516
227 lines
8.5 KiB
C++
227 lines
8.5 KiB
C++
//===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZRegisterInfo.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZSubtarget.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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using namespace llvm;
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#define GET_REGINFO_TARGET_DESC
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#include "SystemZGenRegisterInfo.inc"
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SystemZRegisterInfo::SystemZRegisterInfo()
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: SystemZGenRegisterInfo(SystemZ::R14D) {}
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const MCPhysReg *
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SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
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MF->getFunction()->getAttributes().hasAttrSomewhere(
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Attribute::SwiftError))
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return CSR_SystemZ_SwiftError_SaveList;
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return CSR_SystemZ_SaveList;
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}
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const uint32_t *
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SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
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MF.getFunction()->getAttributes().hasAttrSomewhere(
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Attribute::SwiftError))
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return CSR_SystemZ_SwiftError_RegMask;
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return CSR_SystemZ_RegMask;
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}
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BitVector
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SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const SystemZFrameLowering *TFI = getFrameLowering(MF);
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if (TFI->hasFP(MF)) {
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// R11D is the frame pointer. Reserve all aliases.
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Reserved.set(SystemZ::R11D);
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Reserved.set(SystemZ::R11L);
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Reserved.set(SystemZ::R11H);
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Reserved.set(SystemZ::R10Q);
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}
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// R15D is the stack pointer. Reserve all aliases.
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Reserved.set(SystemZ::R15D);
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Reserved.set(SystemZ::R15L);
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Reserved.set(SystemZ::R15H);
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Reserved.set(SystemZ::R14Q);
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// A0 and A1 hold the thread pointer.
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Reserved.set(SystemZ::A0);
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Reserved.set(SystemZ::A1);
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return Reserved;
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}
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void
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SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
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MachineBasicBlock &MBB = *MI->getParent();
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MachineFunction &MF = *MBB.getParent();
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auto *TII =
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static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
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const SystemZFrameLowering *TFI = getFrameLowering(MF);
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DebugLoc DL = MI->getDebugLoc();
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// Decompose the frame index into a base and offset.
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int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
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unsigned BasePtr;
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int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
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MI->getOperand(FIOperandNum + 1).getImm());
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// Special handling of dbg_value instructions.
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if (MI->isDebugValue()) {
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MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
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MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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return;
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}
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// See if the offset is in range, or if an equivalent instruction that
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// accepts the offset exists.
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unsigned Opcode = MI->getOpcode();
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unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
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if (OpcodeForOffset) {
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if (OpcodeForOffset == SystemZ::LE &&
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MF.getSubtarget<SystemZSubtarget>().hasVector()) {
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// If LE is ok for offset, use LDE instead on z13.
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OpcodeForOffset = SystemZ::LDE32;
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}
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MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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}
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else {
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// Create an anchor point that is in range. Start at 0xffff so that
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// can use LLILH to load the immediate.
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int64_t OldOffset = Offset;
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int64_t Mask = 0xffff;
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do {
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Offset = OldOffset & Mask;
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OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
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Mask >>= 1;
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assert(Mask && "One offset must be OK");
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} while (!OpcodeForOffset);
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unsigned ScratchReg =
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MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
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int64_t HighOffset = OldOffset - Offset;
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if (MI->getDesc().TSFlags & SystemZII::HasIndex
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&& MI->getOperand(FIOperandNum + 2).getReg() == 0) {
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// Load the offset into the scratch register and use it as an index.
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// The scratch register then dies here.
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TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
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MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
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false, false, true);
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} else {
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// Load the anchor address into a scratch register.
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unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
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if (LAOpcode)
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BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
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.addReg(BasePtr).addImm(HighOffset).addReg(0);
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else {
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// Load the high offset into the scratch register and use it as
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// an index.
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TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
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BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
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.addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
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}
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// Use the scratch register as the base. It then dies here.
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MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
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false, false, true);
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}
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}
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MI->setDesc(TII->get(OpcodeForOffset));
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MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
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const TargetRegisterClass *SrcRC,
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unsigned SubReg,
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const TargetRegisterClass *DstRC,
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unsigned DstSubReg,
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const TargetRegisterClass *NewRC,
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LiveIntervals &LIS) const {
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assert (MI->isCopy() && "Only expecting COPY instructions");
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// Coalesce anything which is not a COPY involving a subreg to/from GR128.
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if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
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(getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
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return true;
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// Allow coalescing of a GR128 subreg COPY only if the live ranges are small
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// and local to one MBB with not too much interferring registers. Otherwise
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// regalloc may run out of registers.
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unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
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unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
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unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
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LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
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LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
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// Check that the two virtual registers are local to MBB.
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MachineBasicBlock *MBB = MI->getParent();
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if (LIS.isLiveInToMBB(IntGR128, MBB) || LIS.isLiveOutOfMBB(IntGR128, MBB) ||
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LIS.isLiveInToMBB(IntGRNar, MBB) || LIS.isLiveOutOfMBB(IntGRNar, MBB))
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return false;
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// Find the first and last MIs of the registers.
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MachineInstr *FirstMI = nullptr, *LastMI = nullptr;
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if (WideOpNo == 1) {
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FirstMI = LIS.getInstructionFromIndex(IntGR128.beginIndex());
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LastMI = LIS.getInstructionFromIndex(IntGRNar.endIndex());
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} else {
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FirstMI = LIS.getInstructionFromIndex(IntGRNar.beginIndex());
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LastMI = LIS.getInstructionFromIndex(IntGR128.endIndex());
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}
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assert (FirstMI && LastMI && "No instruction from index?");
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// Check if coalescing seems safe by finding the set of clobbered physreg
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// pairs in the region.
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BitVector PhysClobbered(getNumRegs());
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MachineBasicBlock::iterator MII = FirstMI, MEE = LastMI;
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MEE++;
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for (; MII != MEE; ++MII) {
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for (const MachineOperand &MO : MII->operands())
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if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
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for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
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SI.isValid(); ++SI)
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if (NewRC->contains(*SI)) {
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PhysClobbered.set(*SI);
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break;
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}
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}
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}
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// Demand an arbitrary margin of free regs.
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unsigned const DemandedFreeGR128 = 3;
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if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
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return false;
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return true;
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}
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unsigned
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SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const SystemZFrameLowering *TFI = getFrameLowering(MF);
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return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
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}
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