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4893e095df
This patch teaches llvm-mca how to identify register writes that implicitly zero the upper portion of a super-register. On X86-64, a general purpose register is implemented in hardware as a 64-bit register. Quoting the Intel 64 Software Developer's Manual: "an update to the lower 32 bits of a 64 bit integer register is architecturally defined to zero extend the upper 32 bits". Also, a write to an XMM register performed by an AVX instruction implicitly zeroes the upper 128 bits of the aliasing YMM register. This patch adds a new method named clearsSuperRegisters to the MCInstrAnalysis interface to help identify instructions that implicitly clear the upper portion of a super-register. The rest of the patch teaches llvm-mca how to use that new method to obtain the information, and update the register dependencies accordingly. I compared the kernels from tests clear-super-register-1.s and clear-super-register-2.s against the output from perf on btver2. Previously there was a large discrepancy between the estimated IPC and the measured IPC. Now the differences are mostly in the noise. Differential Revision: https://reviews.llvm.org/D48225 llvm-svn: 335113
100 lines
3.4 KiB
C++
100 lines
3.4 KiB
C++
//===- llvm/MC/MCInstrAnalysis.h - InstrDesc target hooks -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MCInstrAnalysis class which the MCTargetDescs can
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// derive from to give additional information to MC.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCINSTRANALYSIS_H
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#define LLVM_MC_MCINSTRANALYSIS_H
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include <cstdint>
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namespace llvm {
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class MCRegisterInfo;
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class MCInstrAnalysis {
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protected:
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friend class Target;
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const MCInstrInfo *Info;
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public:
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MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {}
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virtual ~MCInstrAnalysis() = default;
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virtual bool isBranch(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isBranch();
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}
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virtual bool isConditionalBranch(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isConditionalBranch();
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}
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virtual bool isUnconditionalBranch(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isUnconditionalBranch();
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}
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virtual bool isIndirectBranch(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isIndirectBranch();
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}
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virtual bool isCall(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isCall();
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}
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virtual bool isReturn(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isReturn();
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}
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virtual bool isTerminator(const MCInst &Inst) const {
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return Info->get(Inst.getOpcode()).isTerminator();
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}
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/// Returns true if at least one of the register writes performed by
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/// \param Inst implicitly clears the upper portion of all super-registers.
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///
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/// Example: on X86-64, a write to EAX implicitly clears the upper half of
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/// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit
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/// instruction implicitly clears the upper portion of the correspondent
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/// YMM register.
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///
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/// This method also updates an APInt which is used as mask of register
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/// writes. There is one bit for every explicit/implicit write performed by
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/// the instruction. If a write implicitly clears its super-registers, then
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/// the corresponding bit is set (vic. the corresponding bit is cleared).
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///
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/// The first bits in the APint are related to explicit writes. The remaining
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/// bits are related to implicit writes. The sequence of writes follows the
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/// machine operand sequence. For implicit writes, the sequence is defined by
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/// the MCInstrDesc.
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///
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/// The assumption is that the bit-width of the APInt is correctly set by
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/// the caller. The default implementation conservatively assumes that none of
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/// the writes clears the upper portion of a super-register.
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virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI,
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const MCInst &Inst,
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APInt &Writes) const;
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/// Given a branch instruction try to get the address the branch
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/// targets. Return true on success, and the address in Target.
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virtual bool
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evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
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uint64_t &Target) const;
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};
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} // end namespace llvm
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#endif // LLVM_MC_MCINSTRANALYSIS_H
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