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- check that -mcpu=slm uses the call register indirect optimization - check that -mcpu=slm runs the scheduler - check that -mcpu=slm supports the movbe instruction llvm-svn: 190814
56 lines
1.6 KiB
LLVM
56 lines
1.6 KiB
LLVM
; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck -check-prefix=ATOM32 %s
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; RUN: llc < %s -mcpu=core2 -mtriple=i686-linux | FileCheck -check-prefix=ATOM-NOT32 %s
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; RUN: llc < %s -mcpu=atom -mtriple=x86_64-linux | FileCheck -check-prefix=ATOM64 %s
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; RUN: llc < %s -mcpu=core2 -mtriple=x86_64-linux | FileCheck -check-prefix=ATOM-NOT64 %s
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; RUN: llc < %s -mcpu=slm -mtriple=i686-linux | FileCheck -check-prefix=SLM32 %s
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; RUN: llc < %s -mcpu=slm -mtriple=x86_64-linux | FileCheck -check-prefix=SLM64 %s
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; fn_ptr.ll
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%class.A = type { i32 (...)** }
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define i32 @test1() #0 {
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;ATOM-LABEL: test1:
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entry:
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%call = tail call %class.A* @_Z3facv()
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%0 = bitcast %class.A* %call to void (%class.A*)***
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%vtable = load void (%class.A*)*** %0, align 8
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%1 = load void (%class.A*)** %vtable, align 8
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;ATOM32: movl (%ecx), %ecx
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;ATOM32: calll *%ecx
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;ATOM-NOT32: calll *(%ecx)
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;ATOM64: movq (%rcx), %rcx
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;ATOM64: callq *%rcx
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;ATOM-NOT64: callq *(%rcx)
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;SLM32: movl (%ecx), %ecx
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;SLM32: calll *%ecx
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;SLM64: movq (%rcx), %rcx
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;SLM64: callq *%rcx
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tail call void %1(%class.A* %call)
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ret i32 0
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}
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declare %class.A* @_Z3facv() #1
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; virt_fn.ll
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@p = external global void (i32)**
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define i32 @test2() #0 {
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;ATOM-LABEL: test2:
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entry:
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%0 = load void (i32)*** @p, align 8
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%1 = load void (i32)** %0, align 8
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;ATOM32: movl (%eax), %eax
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;ATOM32: calll *%eax
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;ATOM-NOT: calll *(%eax)
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;ATOM64: movq (%rax), %rax
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;ATOM64: callq *%rax
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;ATOM-NOT64: callq *(%rax)
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;SLM32: movl (%eax), %eax
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;SLM32: calll *%eax
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;SLM64: movq (%rax), %rax
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;SLM64: callq *%rax
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tail call void %1(i32 2)
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ret i32 0
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}
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