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e3e67d4a0a
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
33 lines
884 B
LLVM
33 lines
884 B
LLVM
; RUN: llc -mtriple x86_64-linux -mcpu core2 -verify-machineinstrs %s -o - | FileCheck %s
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define i32 @f(i1 %foo, i16* %tm_year2, i8* %bar, i16 %zed, i32 %zed2) {
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entry:
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br i1 %foo, label %return, label %if.end
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if.end:
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%rem = srem i32 %zed2, 100
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%conv3 = trunc i32 %rem to i16
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store i16 %conv3, i16* %tm_year2
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%sext = shl i32 %rem, 16
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%conv5 = ashr exact i32 %sext, 16
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%div = sdiv i32 %conv5, 10
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%conv6 = trunc i32 %div to i8
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store i8 %conv6, i8* %bar
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br label %return
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return:
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%retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ]
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ret i32 %retval.0
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}
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; We were miscompiling this and using %ax instead of %cx in the movw
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; in the following sequence:
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; movswl %cx, %ecx
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; movw %cx, (%rsi)
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; movslq %ecx, %rcx
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;
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; We can't produce the above sequence without special SD-level
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; heuristics. Now we produce this:
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; CHECK: movw %ax, (%rsi)
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; CHECK: cwtl
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; CHECK: cltq
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