mirror of
https://github.com/RPCS3/llvm-mirror.git
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479 lines
8.0 KiB
LLVM
479 lines
8.0 KiB
LLVM
; RUN: opt %s -jump-threading -S | FileCheck %s
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declare i32 @f1()
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declare i32 @f2()
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declare void @f3()
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define i32 @test1(i1 %cond) {
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; CHECK: @test1
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br i1 %cond, label %T1, label %F1
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T1:
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%v1 = call i32 @f1()
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br label %Merge
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F1:
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%v2 = call i32 @f2()
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br label %Merge
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Merge:
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%A = phi i1 [true, %T1], [false, %F1]
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%B = phi i32 [%v1, %T1], [%v2, %F1]
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br i1 %A, label %T2, label %F2
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T2:
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; CHECK: T2:
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; CHECK: ret i32 %v1
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call void @f3()
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ret i32 %B
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F2:
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; CHECK: F2:
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; CHECK: ret i32 %v2
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ret i32 %B
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}
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;; cond is known false on Entry -> F1 edge!
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define i32 @test2(i1 %cond) {
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; CHECK: @test2
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Entry:
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br i1 %cond, label %T1, label %F1
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T1:
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; CHECK: %v1 = call i32 @f1()
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; CHECK: ret i32 47
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%v1 = call i32 @f1()
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br label %Merge
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F1:
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br i1 %cond, label %Merge, label %F2
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Merge:
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%B = phi i32 [47, %T1], [192, %F1]
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ret i32 %B
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F2:
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call void @f3()
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ret i32 12
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}
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; Undef handling.
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define i32 @test3(i1 %cond) {
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; CHECK: @test3
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; CHECK-NEXT: T1:
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; CHECK-NEXT: ret i32 42
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br i1 undef, label %T1, label %F1
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T1:
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ret i32 42
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F1:
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ret i32 17
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}
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define i32 @test4(i1 %cond, i1 %cond2) {
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; CHECK: @test4
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br i1 %cond, label %T1, label %F1
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T1:
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; CHECK: %v1 = call i32 @f1()
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; CHECK-NEXT: br label %T
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%v1 = call i32 @f1()
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br label %Merge
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F1:
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%v2 = call i32 @f2()
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; CHECK: %v2 = call i32 @f2()
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; CHECK-NEXT: br i1 %cond2,
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br label %Merge
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Merge:
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%A = phi i1 [undef, %T1], [%cond2, %F1]
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%B = phi i32 [%v1, %T1], [%v2, %F1]
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br i1 %A, label %T2, label %F2
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T2:
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call void @f3()
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ret i32 %B
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F2:
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ret i32 %B
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}
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;; This tests that the branch in 'merge' can be cloned up into T1.
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define i32 @test5(i1 %cond, i1 %cond2) {
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; CHECK: @test5
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br i1 %cond, label %T1, label %F1
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T1:
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; CHECK: T1:
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; CHECK-NEXT: %v1 = call i32 @f1()
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; CHECK-NEXT: %cond3 = icmp eq i32 %v1, 412
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; CHECK-NEXT: br i1 %cond3, label %T2, label %F2
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%v1 = call i32 @f1()
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%cond3 = icmp eq i32 %v1, 412
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br label %Merge
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F1:
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%v2 = call i32 @f2()
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br label %Merge
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Merge:
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%A = phi i1 [%cond3, %T1], [%cond2, %F1]
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%B = phi i32 [%v1, %T1], [%v2, %F1]
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br i1 %A, label %T2, label %F2
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T2:
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call void @f3()
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ret i32 %B
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F2:
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ret i32 %B
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}
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;; Lexically duplicated conditionals should be threaded.
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define i32 @test6(i32 %A) {
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; CHECK: @test6
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%tmp455 = icmp eq i32 %A, 42
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br i1 %tmp455, label %BB1, label %BB2
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; CHECK: call i32 @f2()
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; CHECK-NEXT: ret i32 3
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; CHECK: call i32 @f1()
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; CHECK-NOT: br
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; CHECK: call void @f3()
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; CHECK-NOT: br
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; CHECK: ret i32 4
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BB2:
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call i32 @f1()
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br label %BB1
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BB1:
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%tmp459 = icmp eq i32 %A, 42
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br i1 %tmp459, label %BB3, label %BB4
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BB3:
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call i32 @f2()
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ret i32 3
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BB4:
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call void @f3()
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ret i32 4
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}
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;; This tests that the branch in 'merge' can be cloned up into T1.
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;; rdar://7367025
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define i32 @test7(i1 %cond, i1 %cond2) {
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Entry:
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; CHECK: @test7
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%v1 = call i32 @f1()
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br i1 %cond, label %Merge, label %F1
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F1:
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%v2 = call i32 @f2()
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br label %Merge
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Merge:
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%B = phi i32 [%v1, %Entry], [%v2, %F1]
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%M = icmp ne i32 %B, %v1
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%N = icmp eq i32 %B, 47
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%O = and i1 %M, %N
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br i1 %O, label %T2, label %F2
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; CHECK: Merge:
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; CHECK-NOT: phi
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; CHECK-NEXT: %v2 = call i32 @f2()
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T2:
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call void @f3()
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ret i32 %B
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F2:
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ret i32 %B
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; CHECK: F2:
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; CHECK-NEXT: phi i32
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}
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declare i1 @test8a()
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define i32 @test8b(i1 %cond, i1 %cond2) {
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; CHECK: @test8b
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T0:
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%A = call i1 @test8a()
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br i1 %A, label %T1, label %F1
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; CHECK: T0:
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; CHECK-NEXT: call
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; CHECK-NEXT: br i1 %A, label %T1, label %Y
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T1:
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%B = call i1 @test8a()
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br i1 %B, label %T2, label %F1
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; CHECK: T1:
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; CHECK-NEXT: call
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; CHECK-NEXT: br i1 %B, label %T2, label %Y
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T2:
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%C = call i1 @test8a()
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br i1 %cond, label %T3, label %F1
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; CHECK: T2:
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; CHECK-NEXT: call
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; CHECK-NEXT: br i1 %cond, label %T3, label %Y
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T3:
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ret i32 0
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F1:
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%D = phi i32 [0, %T0], [0, %T1], [1, %T2]
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%E = icmp eq i32 %D, 1
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%F = and i1 %E, %cond
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br i1 %F, label %X, label %Y
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X:
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call i1 @test8a()
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ret i32 1
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Y:
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ret i32 2
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}
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;;; Verify that we can handle constraint propagation through "xor x, 1".
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define i32 @test9(i1 %cond, i1 %cond2) {
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Entry:
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; CHECK: @test9
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%v1 = call i32 @f1()
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br i1 %cond, label %Merge, label %F1
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; CHECK: Entry:
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; CHECK-NEXT: %v1 = call i32 @f1()
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; CHECK-NEXT: br i1 %cond, label %F2, label %Merge
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F1:
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%v2 = call i32 @f2()
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br label %Merge
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Merge:
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%B = phi i32 [%v1, %Entry], [%v2, %F1]
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%M = icmp eq i32 %B, %v1
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%M1 = xor i1 %M, 1
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%N = icmp eq i32 %B, 47
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%O = and i1 %M1, %N
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br i1 %O, label %T2, label %F2
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; CHECK: Merge:
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; CHECK-NOT: phi
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; CHECK-NEXT: %v2 = call i32 @f2()
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T2:
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%Q = zext i1 %M to i32
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ret i32 %Q
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F2:
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ret i32 %B
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; CHECK: F2:
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; CHECK-NEXT: phi i32
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}
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; CHECK: @test10
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declare i32 @test10f1()
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declare i32 @test10f2()
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declare void @test10f3()
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;; Non-local condition threading.
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define i32 @test10g(i1 %cond) {
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; CHECK: @test10g
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; CHECK-NEXT: br i1 %cond, label %T2, label %F2
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br i1 %cond, label %T1, label %F1
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T1:
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%v1 = call i32 @test10f1()
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br label %Merge
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; CHECK: %v1 = call i32 @test10f1()
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; CHECK-NEXT: call void @f3()
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; CHECK-NEXT: ret i32 %v1
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F1:
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%v2 = call i32 @test10f2()
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br label %Merge
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Merge:
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%B = phi i32 [%v1, %T1], [%v2, %F1]
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br i1 %cond, label %T2, label %F2
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T2:
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call void @f3()
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ret i32 %B
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F2:
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ret i32 %B
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}
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; Impossible conditional constraints should get threaded. BB3 is dead here.
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define i32 @test11(i32 %A) {
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; CHECK: @test11
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; CHECK-NEXT: icmp
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; CHECK-NEXT: br i1 %tmp455, label %BB4, label %BB2
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%tmp455 = icmp eq i32 %A, 42
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br i1 %tmp455, label %BB1, label %BB2
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BB2:
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; CHECK: call i32 @f1()
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; CHECK-NEXT: ret i32 %C
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%C = call i32 @f1()
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ret i32 %C
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BB1:
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%tmp459 = icmp eq i32 %A, 43
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br i1 %tmp459, label %BB3, label %BB4
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BB3:
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call i32 @f2()
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ret i32 3
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BB4:
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call void @f3()
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ret i32 4
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}
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;; Correlated value through boolean expression. GCC PR18046.
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define void @test12(i32 %A) {
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; CHECK: @test12
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entry:
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%cond = icmp eq i32 %A, 0
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br i1 %cond, label %bb, label %bb1
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; Should branch to the return block instead of through BB1.
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; CHECK: entry:
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; CHECK-NEXT: %cond = icmp eq i32 %A, 0
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; CHECK-NEXT: br i1 %cond, label %bb1, label %return
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bb:
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%B = call i32 @test10f2()
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br label %bb1
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bb1:
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%C = phi i32 [ %A, %entry ], [ %B, %bb ]
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%cond4 = icmp eq i32 %C, 0
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br i1 %cond4, label %bb2, label %return
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; CHECK: bb1:
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; CHECK-NEXT: %B = call i32 @test10f2()
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; CHECK-NEXT: %cond4 = icmp eq i32 %B, 0
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; CHECK-NEXT: br i1 %cond4, label %bb2, label %return
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bb2:
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%D = call i32 @test10f2()
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ret void
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return:
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ret void
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}
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;; Duplicate condition to avoid xor of cond.
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;; rdar://7391699
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define i32 @test13(i1 %cond, i1 %cond2) {
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Entry:
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; CHECK: @test13
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%v1 = call i32 @f1()
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br i1 %cond, label %Merge, label %F1
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F1:
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br label %Merge
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Merge:
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%B = phi i1 [true, %Entry], [%cond2, %F1]
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%C = phi i32 [192, %Entry], [%v1, %F1]
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%M = icmp eq i32 %C, 192
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%N = xor i1 %B, %M
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br i1 %N, label %T2, label %F2
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T2:
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ret i32 123
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F2:
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ret i32 %v1
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; CHECK: br i1 %cond, label %F2, label %Merge
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; CHECK: Merge:
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; CHECK-NEXT: %M = icmp eq i32 %v1, 192
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; CHECK-NEXT: %N = xor i1 %cond2, %M
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; CHECK-NEXT: br i1 %N, label %T2, label %F2
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}
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; CHECK: @test14
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define i32 @test14(i32 %in) {
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entry:
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%A = icmp eq i32 %in, 0
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; CHECK: br i1 %A, label %right_ret, label %merge
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br i1 %A, label %left, label %right
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; CHECK-NOT: left:
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left:
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br label %merge
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; CHECK-NOT: right:
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right:
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%B = call i32 @f1()
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br label %merge
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merge:
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; CHECK-NOT: %C = phi i32 [%in, %left], [%B, %right]
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%C = phi i32 [%in, %left], [%B, %right]
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%D = add i32 %C, 1
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%E = icmp eq i32 %D, 2
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br i1 %E, label %left_ret, label %right_ret
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; CHECK: left_ret:
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left_ret:
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ret i32 0
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right_ret:
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ret i32 1
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}
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; PR5652
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; CHECK: @test15
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define i32 @test15(i32 %len) {
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entry:
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; CHECK: icmp ult i32 %len, 13
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%tmp = icmp ult i32 %len, 13
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br i1 %tmp, label %check, label %exit0
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exit0:
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ret i32 0
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check:
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%tmp9 = icmp ult i32 %len, 21
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br i1 %tmp9, label %exit1, label %exit2
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exit2:
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; CHECK-NOT: ret i32 2
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ret i32 2
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exit1:
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ret i32 1
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; CHECK: }
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}
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