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293 lines
9.9 KiB
C++
293 lines
9.9 KiB
C++
//===-- SparcV9TargetMachine.cpp - SparcV9 Target Machine Implementation --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Primary interface to machine description for the UltraSPARC. Primarily just
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// initializes machine-dependent parameters in class TargetMachine, and creates
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// machine-dependent subclasses for classes such as TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Function.h"
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#include "llvm/PassManager.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/IntrinsicLowering.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include "MappingInfo.h"
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#include "MachineFunctionInfo.h"
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#include "MachineCodeForInstruction.h"
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#include "SparcV9Internals.h"
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#include "SparcV9TargetMachine.h"
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#include "SparcV9BurgISel.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
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// Build the MachineInstruction Description Array...
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const TargetInstrDescriptor llvm::SparcV9MachineInstrDesc[] = {
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
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ImplicitRegUseList, ImplicitRegUseList },
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#include "SparcV9Instr.def"
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};
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//---------------------------------------------------------------------------
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// Command line options to control choice of code generation passes.
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//---------------------------------------------------------------------------
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namespace llvm {
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bool EmitMappingInfo = false;
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}
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namespace {
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cl::opt<bool> DisableSched("disable-sched",
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cl::desc("Disable local scheduling pass"));
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cl::opt<bool> DisablePeephole("disable-peephole",
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cl::desc("Disable peephole optimization pass"));
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cl::opt<bool, true> EmitMappingInfoOpt("enable-maps",
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cl::location(EmitMappingInfo),
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cl::init(false),
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cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
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cl::opt<bool> EnableModSched("enable-modsched",
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cl::desc("Enable modulo scheduling pass instead of local scheduling"), cl::Hidden);
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// Register the target.
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RegisterTarget<SparcV9TargetMachine> X("sparcv9", " SPARC V9");
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}
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unsigned SparcV9TargetMachine::getJITMatchQuality() {
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#if defined(__sparcv9)
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return 10;
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#else
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return 0;
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#endif
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}
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unsigned SparcV9TargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "sparcv9-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "sparcv9-")
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return 20;
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if (M.getEndianness() == Module::BigEndian &&
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M.getPointerSize() == Module::Pointer64)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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//===---------------------------------------------------------------------===//
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// Code generation/destruction passes
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//===---------------------------------------------------------------------===//
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namespace {
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class ConstructMachineFunction : public FunctionPass {
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TargetMachine &Target;
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public:
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ConstructMachineFunction(TargetMachine &T) : Target(T) {}
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const char *getPassName() const {
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return "ConstructMachineFunction";
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}
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bool runOnFunction(Function &F) {
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MachineFunction::construct(&F, Target).getInfo<SparcV9FunctionInfo>()->CalculateArgSize();
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return false;
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}
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};
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struct DestroyMachineFunction : public FunctionPass {
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const char *getPassName() const { return "DestroyMachineFunction"; }
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static void freeMachineCode(Instruction &I) {
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MachineCodeForInstruction::destroy(&I);
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}
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bool runOnFunction(Function &F) {
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
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MachineCodeForInstruction::get(I).dropAllReferences();
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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for_each(FI->begin(), FI->end(), freeMachineCode);
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MachineFunction::destruct(&F);
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return false;
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}
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};
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FunctionPass *createMachineCodeConstructionPass(TargetMachine &Target) {
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return new ConstructMachineFunction(Target);
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}
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}
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FunctionPass *llvm::createSparcV9MachineCodeDestructionPass() {
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return new DestroyMachineFunction();
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}
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SparcV9TargetMachine::SparcV9TargetMachine(const Module &M,
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IntrinsicLowering *il)
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: TargetMachine("UltraSparcV9-Native", il, false),
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schedInfo(*this),
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regInfo(*this),
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frameInfo(*this),
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jitInfo(*this) {
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}
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/// addPassesToEmitAssembly - This method controls the entire code generation
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/// process for the ultra sparc.
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///
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bool
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SparcV9TargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
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{
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// Replace malloc and free instructions with library calls.
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PM.add(createLowerAllocationsPass());
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// FIXME: implement the switch instruction in the instruction selector.
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PM.add(createLowerSwitchPass());
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// FIXME: implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// decompose multi-dimensional array references into single-dim refs
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PM.add(createDecomposeMultiDimRefsPass());
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// Lower LLVM code to the form expected by the SPARCv9 instruction selector.
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PM.add(createPreSelectionPass(*this));
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PM.add(createLowerSelectPass());
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// If the user's trying to read the generated code, they'll need to see the
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// transformed input.
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if (PrintMachineCode)
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PM.add(new PrintModulePass());
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// Construct and initialize the MachineFunction object for this fn.
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PM.add(createMachineCodeConstructionPass(*this));
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// Insert empty stackslots in the stack frame of each function
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// so %fp+offset-8 and %fp+offset-16 are empty slots now!
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PM.add(createStackSlotsPass(*this));
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PM.add(createSparcV9BurgInstSelector(*this));
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if (!DisableSched)
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PM.add(createInstructionSchedulingWithSSAPass(*this));
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if(PrintMachineCode && EnableModSched)
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PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before modulo scheduling:\n"));
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//Use ModuloScheduling if enabled, otherwise use local scheduling if not disabled.
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if(EnableModSched)
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PM.add(createModuloSchedulingPass(*this));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
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PM.add(getRegisterAllocator(*this));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr, "After reg alloc:\n"));
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PM.add(createPrologEpilogInsertionPass());
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if (!DisablePeephole)
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PM.add(createPeepholeOptsPass(*this));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr, "Final code:\n"));
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if (EmitMappingInfo) {
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PM.add(createInternalGlobalMapperPass());
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PM.add(getMappingInfoAsmPrinterPass(Out));
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}
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// Output assembly language to the .s file. Assembly emission is split into
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// two parts: Function output and Global value output. This is because
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// function output is pipelined with all of the rest of code generation stuff,
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// allowing machine code representations for functions to be free'd after the
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// function has been emitted.
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PM.add(createAsmPrinterPass(Out, *this));
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// Free machine-code IR which is no longer needed:
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PM.add(createSparcV9MachineCodeDestructionPass());
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// Emit bytecode to the assembly file into its special section next
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if (EmitMappingInfo)
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PM.add(createBytecodeAsmPrinterPass(Out));
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return false;
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}
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/// addPassesToJITCompile - This method controls the JIT method of code
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/// generation for the UltraSparcV9.
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///
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void SparcV9JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// Replace malloc and free instructions with library calls.
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PM.add(createLowerAllocationsPass());
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// FIXME: implement the switch instruction in the instruction selector.
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PM.add(createLowerSwitchPass());
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// FIXME: implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// decompose multi-dimensional array references into single-dim refs
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PM.add(createDecomposeMultiDimRefsPass());
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// Lower LLVM code to the form expected by the SPARCv9 instruction selector.
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PM.add(createPreSelectionPass(TM));
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PM.add(createLowerSelectPass());
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// If the user's trying to read the generated code, they'll need to see the
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// transformed input.
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if (PrintMachineCode)
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PM.add(new PrintFunctionPass());
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// Construct and initialize the MachineFunction object for this fn.
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PM.add(createMachineCodeConstructionPass(TM));
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PM.add(createSparcV9BurgInstSelector(TM));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
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PM.add(getRegisterAllocator(TM));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr, "After reg alloc:\n"));
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PM.add(createPrologEpilogInsertionPass());
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if (!DisablePeephole)
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PM.add(createPeepholeOptsPass(TM));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr, "Final code:\n"));
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}
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