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699 lines
20 KiB
Plaintext
699 lines
20 KiB
Plaintext
//===---------------------------------------------------------------------===//
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// Random ideas for the X86 backend: SSE-specific stuff.
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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When compiled with unsafemath enabled, "main" should enable SSE DAZ mode and
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other fast SSE modes.
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//===---------------------------------------------------------------------===//
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Think about doing i64 math in SSE regs.
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//===---------------------------------------------------------------------===//
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This testcase should have no SSE instructions in it, and only one load from
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a constant pool:
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double %test3(bool %B) {
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%C = select bool %B, double 123.412, double 523.01123123
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ret double %C
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}
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Currently, the select is being lowered, which prevents the dag combiner from
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turning 'select (load CPI1), (load CPI2)' -> 'load (select CPI1, CPI2)'
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The pattern isel got this one right.
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//===---------------------------------------------------------------------===//
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SSE doesn't have [mem] op= reg instructions. If we have an SSE instruction
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like this:
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X += y
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and the register allocator decides to spill X, it is cheaper to emit this as:
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Y += [xslot]
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store Y -> [xslot]
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than as:
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tmp = [xslot]
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tmp += y
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store tmp -> [xslot]
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..and this uses one fewer register (so this should be done at load folding
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time, not at spiller time). *Note* however that this can only be done
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if Y is dead. Here's a testcase:
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%.str_3 = external global [15 x sbyte] ; <[15 x sbyte]*> [#uses=0]
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implementation ; Functions:
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declare void %printf(int, ...)
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void %main() {
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build_tree.exit:
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br label %no_exit.i7
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no_exit.i7: ; preds = %no_exit.i7, %build_tree.exit
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%tmp.0.1.0.i9 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.34.i18, %no_exit.i7 ] ; <double> [#uses=1]
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%tmp.0.0.0.i10 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.28.i16, %no_exit.i7 ] ; <double> [#uses=1]
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%tmp.28.i16 = add double %tmp.0.0.0.i10, 0.000000e+00
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%tmp.34.i18 = add double %tmp.0.1.0.i9, 0.000000e+00
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br bool false, label %Compute_Tree.exit23, label %no_exit.i7
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Compute_Tree.exit23: ; preds = %no_exit.i7
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tail call void (int, ...)* %printf( int 0 )
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store double %tmp.34.i18, double* null
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ret void
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}
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We currently emit:
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.BBmain_1:
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xorpd %XMM1, %XMM1
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addsd %XMM0, %XMM1
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*** movsd %XMM2, QWORD PTR [%ESP + 8]
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*** addsd %XMM2, %XMM1
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*** movsd QWORD PTR [%ESP + 8], %XMM2
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jmp .BBmain_1 # no_exit.i7
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This is a bugpoint reduced testcase, which is why the testcase doesn't make
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much sense (e.g. its an infinite loop). :)
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//===---------------------------------------------------------------------===//
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SSE should implement 'select_cc' using 'emulated conditional moves' that use
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pcmp/pand/pandn/por to do a selection instead of a conditional branch:
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double %X(double %Y, double %Z, double %A, double %B) {
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%C = setlt double %A, %B
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%z = add double %Z, 0.0 ;; select operand is not a load
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%D = select bool %C, double %Y, double %z
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ret double %D
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}
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We currently emit:
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_X:
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subl $12, %esp
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xorpd %xmm0, %xmm0
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addsd 24(%esp), %xmm0
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movsd 32(%esp), %xmm1
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movsd 16(%esp), %xmm2
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ucomisd 40(%esp), %xmm1
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jb LBB_X_2
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LBB_X_1:
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movsd %xmm0, %xmm2
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LBB_X_2:
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movsd %xmm2, (%esp)
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fldl (%esp)
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addl $12, %esp
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ret
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//===---------------------------------------------------------------------===//
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It's not clear whether we should use pxor or xorps / xorpd to clear XMM
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registers. The choice may depend on subtarget information. We should do some
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more experiments on different x86 machines.
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//===---------------------------------------------------------------------===//
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Currently the x86 codegen isn't very good at mixing SSE and FPStack
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code:
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unsigned int foo(double x) { return x; }
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foo:
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subl $20, %esp
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movsd 24(%esp), %xmm0
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movsd %xmm0, 8(%esp)
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fldl 8(%esp)
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fisttpll (%esp)
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movl (%esp), %eax
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addl $20, %esp
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ret
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This will be solved when we go to a dynamic programming based isel.
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//===---------------------------------------------------------------------===//
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Should generate min/max for stuff like:
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void minf(float a, float b, float *X) {
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*X = a <= b ? a : b;
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}
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Make use of floating point min / max instructions. Perhaps introduce ISD::FMIN
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and ISD::FMAX node types?
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//===---------------------------------------------------------------------===//
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The first BB of this code:
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declare bool %foo()
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int %bar() {
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%V = call bool %foo()
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br bool %V, label %T, label %F
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T:
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ret int 1
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F:
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call bool %foo()
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ret int 12
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}
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compiles to:
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_bar:
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subl $12, %esp
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call L_foo$stub
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xorb $1, %al
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testb %al, %al
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jne LBB_bar_2 # F
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It would be better to emit "cmp %al, 1" than a xor and test.
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//===---------------------------------------------------------------------===//
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Lower memcpy / memset to a series of SSE 128 bit move instructions when it's
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feasible.
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//===---------------------------------------------------------------------===//
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Teach the coalescer to commute 2-addr instructions, allowing us to eliminate
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the reg-reg copy in this example:
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float foo(int *x, float *y, unsigned c) {
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float res = 0.0;
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unsigned i;
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for (i = 0; i < c; i++) {
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float xx = (float)x[i];
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xx = xx * y[i];
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xx += res;
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res = xx;
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}
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return res;
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}
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LBB_foo_3: # no_exit
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cvtsi2ss %XMM0, DWORD PTR [%EDX + 4*%ESI]
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mulss %XMM0, DWORD PTR [%EAX + 4*%ESI]
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addss %XMM0, %XMM1
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inc %ESI
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cmp %ESI, %ECX
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**** movaps %XMM1, %XMM0
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jb LBB_foo_3 # no_exit
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//===---------------------------------------------------------------------===//
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Codegen:
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if (copysign(1.0, x) == copysign(1.0, y))
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into:
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if (x^y & mask)
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when using SSE.
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//===---------------------------------------------------------------------===//
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Use movhps to update upper 64-bits of a v4sf value. Also movlps on lower half
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of a v4sf value.
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//===---------------------------------------------------------------------===//
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Better codegen for vector_shuffles like this { x, 0, 0, 0 } or { x, 0, x, 0}.
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Perhaps use pxor / xorp* to clear a XMM register first?
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//===---------------------------------------------------------------------===//
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Better codegen for:
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void f(float a, float b, vector float * out) { *out = (vector float){ a, 0.0, 0.0, b}; }
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void f(float a, float b, vector float * out) { *out = (vector float){ a, b, 0.0, 0}; }
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For the later we generate:
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_f:
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pxor %xmm0, %xmm0
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movss 8(%esp), %xmm1
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movaps %xmm0, %xmm2
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unpcklps %xmm1, %xmm2
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movss 4(%esp), %xmm1
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unpcklps %xmm0, %xmm1
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unpcklps %xmm2, %xmm1
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movl 12(%esp), %eax
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movaps %xmm1, (%eax)
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ret
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This seems like it should use shufps, one for each of a & b.
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//===---------------------------------------------------------------------===//
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How to decide when to use the "floating point version" of logical ops? Here are
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some code fragments:
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movaps LCPI5_5, %xmm2
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divps %xmm1, %xmm2
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mulps %xmm2, %xmm3
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mulps 8656(%ecx), %xmm3
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addps 8672(%ecx), %xmm3
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andps LCPI5_6, %xmm2
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andps LCPI5_1, %xmm3
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por %xmm2, %xmm3
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movdqa %xmm3, (%edi)
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movaps LCPI5_5, %xmm1
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divps %xmm0, %xmm1
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mulps %xmm1, %xmm3
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mulps 8656(%ecx), %xmm3
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addps 8672(%ecx), %xmm3
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andps LCPI5_6, %xmm1
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andps LCPI5_1, %xmm3
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orps %xmm1, %xmm3
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movaps %xmm3, 112(%esp)
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movaps %xmm3, (%ebx)
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Due to some minor source change, the later case ended up using orps and movaps
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instead of por and movdqa. Does it matter?
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//===---------------------------------------------------------------------===//
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Use movddup to splat a v2f64 directly from a memory source. e.g.
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#include <emmintrin.h>
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void test(__m128d *r, double A) {
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*r = _mm_set1_pd(A);
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}
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llc:
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_test:
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movsd 8(%esp), %xmm0
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unpcklpd %xmm0, %xmm0
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movl 4(%esp), %eax
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movapd %xmm0, (%eax)
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ret
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icc:
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_test:
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movl 4(%esp), %eax
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movddup 8(%esp), %xmm0
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movapd %xmm0, (%eax)
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ret
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//===---------------------------------------------------------------------===//
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X86RegisterInfo::copyRegToReg() returns X86::MOVAPSrr for VR128. Is it possible
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to choose between movaps, movapd, and movdqa based on types of source and
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destination?
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How about andps, andpd, and pand? Do we really care about the type of the packed
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elements? If not, why not always use the "ps" variants which are likely to be
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shorter.
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//===---------------------------------------------------------------------===//
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We are emitting bad code for this:
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float %test(float* %V, int %I, int %D, float %V) {
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entry:
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%tmp = seteq int %D, 0
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br bool %tmp, label %cond_true, label %cond_false23
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cond_true:
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%tmp3 = getelementptr float* %V, int %I
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%tmp = load float* %tmp3
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%tmp5 = setgt float %tmp, %V
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%tmp6 = tail call bool %llvm.isunordered.f32( float %tmp, float %V )
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%tmp7 = or bool %tmp5, %tmp6
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br bool %tmp7, label %UnifiedReturnBlock, label %cond_next
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cond_next:
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%tmp10 = add int %I, 1
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%tmp12 = getelementptr float* %V, int %tmp10
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%tmp13 = load float* %tmp12
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%tmp15 = setle float %tmp13, %V
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%tmp16 = tail call bool %llvm.isunordered.f32( float %tmp13, float %V )
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%tmp17 = or bool %tmp15, %tmp16
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%retval = select bool %tmp17, float 0.000000e+00, float 1.000000e+00
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ret float %retval
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cond_false23:
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%tmp28 = tail call float %foo( float* %V, int %I, int %D, float %V )
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ret float %tmp28
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UnifiedReturnBlock: ; preds = %cond_true
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ret float 0.000000e+00
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}
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declare bool %llvm.isunordered.f32(float, float)
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declare float %foo(float*, int, int, float)
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It exposes a known load folding problem:
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movss (%edx,%ecx,4), %xmm1
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ucomiss %xmm1, %xmm0
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As well as this:
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LBB_test_2: # cond_next
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movss LCPI1_0, %xmm2
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pxor %xmm3, %xmm3
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ucomiss %xmm0, %xmm1
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jbe LBB_test_6 # cond_next
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LBB_test_5: # cond_next
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movaps %xmm2, %xmm3
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LBB_test_6: # cond_next
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movss %xmm3, 40(%esp)
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flds 40(%esp)
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addl $44, %esp
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ret
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Clearly it's unnecessary to clear %xmm3. It's also not clear why we are emitting
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three moves (movss, movaps, movss).
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//===---------------------------------------------------------------------===//
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External test Nurbs exposed some problems. Look for
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__ZN15Nurbs_SSE_Cubic17TessellateSurfaceE, bb cond_next140. This is what icc
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emits:
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movaps (%edx), %xmm2 #59.21
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movaps (%edx), %xmm5 #60.21
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movaps (%edx), %xmm4 #61.21
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movaps (%edx), %xmm3 #62.21
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movl 40(%ecx), %ebp #69.49
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shufps $0, %xmm2, %xmm5 #60.21
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movl 100(%esp), %ebx #69.20
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movl (%ebx), %edi #69.20
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imull %ebp, %edi #69.49
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addl (%eax), %edi #70.33
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shufps $85, %xmm2, %xmm4 #61.21
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shufps $170, %xmm2, %xmm3 #62.21
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shufps $255, %xmm2, %xmm2 #63.21
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lea (%ebp,%ebp,2), %ebx #69.49
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negl %ebx #69.49
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lea -3(%edi,%ebx), %ebx #70.33
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shll $4, %ebx #68.37
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addl 32(%ecx), %ebx #68.37
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testb $15, %bl #91.13
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jne L_B1.24 # Prob 5% #91.13
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This is the llvm code after instruction scheduling:
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cond_next140 (0xa910740, LLVM BB @0xa90beb0):
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%reg1078 = MOV32ri -3
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%reg1079 = ADD32rm %reg1078, %reg1068, 1, %NOREG, 0
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%reg1037 = MOV32rm %reg1024, 1, %NOREG, 40
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%reg1080 = IMUL32rr %reg1079, %reg1037
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%reg1081 = MOV32rm %reg1058, 1, %NOREG, 0
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%reg1038 = LEA32r %reg1081, 1, %reg1080, -3
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%reg1036 = MOV32rm %reg1024, 1, %NOREG, 32
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%reg1082 = SHL32ri %reg1038, 4
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%reg1039 = ADD32rr %reg1036, %reg1082
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%reg1083 = MOVAPSrm %reg1059, 1, %NOREG, 0
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%reg1034 = SHUFPSrr %reg1083, %reg1083, 170
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%reg1032 = SHUFPSrr %reg1083, %reg1083, 0
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%reg1035 = SHUFPSrr %reg1083, %reg1083, 255
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%reg1033 = SHUFPSrr %reg1083, %reg1083, 85
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%reg1040 = MOV32rr %reg1039
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%reg1084 = AND32ri8 %reg1039, 15
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CMP32ri8 %reg1084, 0
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JE mbb<cond_next204,0xa914d30>
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Still ok. After register allocation:
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cond_next140 (0xa910740, LLVM BB @0xa90beb0):
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%EAX = MOV32ri -3
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%EDX = MOV32rm <fi#3>, 1, %NOREG, 0
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ADD32rm %EAX<def&use>, %EDX, 1, %NOREG, 0
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%EDX = MOV32rm <fi#7>, 1, %NOREG, 0
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%EDX = MOV32rm %EDX, 1, %NOREG, 40
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IMUL32rr %EAX<def&use>, %EDX
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%ESI = MOV32rm <fi#5>, 1, %NOREG, 0
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%ESI = MOV32rm %ESI, 1, %NOREG, 0
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MOV32mr <fi#4>, 1, %NOREG, 0, %ESI
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%EAX = LEA32r %ESI, 1, %EAX, -3
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%ESI = MOV32rm <fi#7>, 1, %NOREG, 0
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%ESI = MOV32rm %ESI, 1, %NOREG, 32
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%EDI = MOV32rr %EAX
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SHL32ri %EDI<def&use>, 4
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ADD32rr %EDI<def&use>, %ESI
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%XMM0 = MOVAPSrm %ECX, 1, %NOREG, 0
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%XMM1 = MOVAPSrr %XMM0
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SHUFPSrr %XMM1<def&use>, %XMM1, 170
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%XMM2 = MOVAPSrr %XMM0
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SHUFPSrr %XMM2<def&use>, %XMM2, 0
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%XMM3 = MOVAPSrr %XMM0
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SHUFPSrr %XMM3<def&use>, %XMM3, 255
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SHUFPSrr %XMM0<def&use>, %XMM0, 85
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%EBX = MOV32rr %EDI
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AND32ri8 %EBX<def&use>, 15
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CMP32ri8 %EBX, 0
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JE mbb<cond_next204,0xa914d30>
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This looks really bad. The problem is shufps is a destructive opcode. Since it
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appears as operand two in more than one shufps ops. It resulted in a number of
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copies. Note icc also suffers from the same problem. Either the instruction
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selector should select pshufd or The register allocator can made the two-address
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to three-address transformation.
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It also exposes some other problems. See MOV32ri -3 and the spills.
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//===---------------------------------------------------------------------===//
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=25500
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LLVM is producing bad code.
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LBB_main_4: # cond_true44
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addps %xmm1, %xmm2
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subps %xmm3, %xmm2
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movaps (%ecx), %xmm4
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movaps %xmm2, %xmm1
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addps %xmm4, %xmm1
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addl $16, %ecx
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incl %edx
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cmpl $262144, %edx
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movaps %xmm3, %xmm2
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movaps %xmm4, %xmm3
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jne LBB_main_4 # cond_true44
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There are two problems. 1) No need to two loop induction variables. We can
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compare against 262144 * 16. 2) Known register coalescer issue. We should
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be able eliminate one of the movaps:
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addps %xmm2, %xmm1 <=== Commute!
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subps %xmm3, %xmm1
|
|
movaps (%ecx), %xmm4
|
|
movaps %xmm1, %xmm1 <=== Eliminate!
|
|
addps %xmm4, %xmm1
|
|
addl $16, %ecx
|
|
incl %edx
|
|
cmpl $262144, %edx
|
|
movaps %xmm3, %xmm2
|
|
movaps %xmm4, %xmm3
|
|
jne LBB_main_4 # cond_true44
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Consider:
|
|
|
|
__m128 test(float a) {
|
|
return _mm_set_ps(0.0, 0.0, 0.0, a*a);
|
|
}
|
|
|
|
This compiles into:
|
|
|
|
movss 4(%esp), %xmm1
|
|
mulss %xmm1, %xmm1
|
|
xorps %xmm0, %xmm0
|
|
movss %xmm1, %xmm0
|
|
ret
|
|
|
|
Because mulss doesn't modify the top 3 elements, the top elements of
|
|
xmm1 are already zero'd. We could compile this to:
|
|
|
|
movss 4(%esp), %xmm0
|
|
mulss %xmm0, %xmm0
|
|
ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Here's a sick and twisted idea. Consider code like this:
|
|
|
|
__m128 test(__m128 a) {
|
|
float b = *(float*)&A;
|
|
...
|
|
return _mm_set_ps(0.0, 0.0, 0.0, b);
|
|
}
|
|
|
|
This might compile to this code:
|
|
|
|
movaps c(%esp), %xmm1
|
|
xorps %xmm0, %xmm0
|
|
movss %xmm1, %xmm0
|
|
ret
|
|
|
|
Now consider if the ... code caused xmm1 to get spilled. This might produce
|
|
this code:
|
|
|
|
movaps c(%esp), %xmm1
|
|
movaps %xmm1, c2(%esp)
|
|
...
|
|
|
|
xorps %xmm0, %xmm0
|
|
movaps c2(%esp), %xmm1
|
|
movss %xmm1, %xmm0
|
|
ret
|
|
|
|
However, since the reload is only used by these instructions, we could
|
|
"fold" it into the uses, producing something like this:
|
|
|
|
movaps c(%esp), %xmm1
|
|
movaps %xmm1, c2(%esp)
|
|
...
|
|
|
|
movss c2(%esp), %xmm0
|
|
ret
|
|
|
|
... saving two instructions.
|
|
|
|
The basic idea is that a reload from a spill slot, can, if only one 4-byte
|
|
chunk is used, bring in 3 zeros the the one element instead of 4 elements.
|
|
This can be used to simplify a variety of shuffle operations, where the
|
|
elements are fixed zeros.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
For this:
|
|
|
|
#include <emmintrin.h>
|
|
void test(__m128d *r, __m128d *A, double B) {
|
|
*r = _mm_loadl_pd(*A, &B);
|
|
}
|
|
|
|
We generates:
|
|
|
|
subl $12, %esp
|
|
movsd 24(%esp), %xmm0
|
|
movsd %xmm0, (%esp)
|
|
movl 20(%esp), %eax
|
|
movapd (%eax), %xmm0
|
|
movlpd (%esp), %xmm0
|
|
movl 16(%esp), %eax
|
|
movapd %xmm0, (%eax)
|
|
addl $12, %esp
|
|
ret
|
|
|
|
icc generates:
|
|
|
|
movl 4(%esp), %edx #3.6
|
|
movl 8(%esp), %eax #3.6
|
|
movapd (%eax), %xmm0 #4.22
|
|
movlpd 12(%esp), %xmm0 #4.8
|
|
movapd %xmm0, (%edx) #4.3
|
|
ret #5.1
|
|
|
|
So icc is smart enough to know that B is in memory so it doesn't load it and
|
|
store it back to stack.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
__m128d test1( __m128d A, __m128d B) {
|
|
return _mm_shuffle_pd(A, B, 0x3);
|
|
}
|
|
|
|
compiles to
|
|
|
|
shufpd $3, %xmm1, %xmm0
|
|
|
|
Perhaps it's better to use unpckhpd instead?
|
|
|
|
unpckhpd %xmm1, %xmm0
|
|
|
|
Don't know if unpckhpd is faster. But it is shorter.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
This code generates ugly code, probably due to costs being off or something:
|
|
|
|
void %test(float* %P, <4 x float>* %P2 ) {
|
|
%xFloat0.688 = load float* %P
|
|
%loadVector37.712 = load <4 x float>* %P2
|
|
%inFloat3.713 = insertelement <4 x float> %loadVector37.712, float 0.000000e+00, uint 3
|
|
store <4 x float> %inFloat3.713, <4 x float>* %P2
|
|
ret void
|
|
}
|
|
|
|
Generates:
|
|
|
|
_test:
|
|
pxor %xmm0, %xmm0
|
|
movd %xmm0, %eax ;; EAX = 0!
|
|
movl 8(%esp), %ecx
|
|
movaps (%ecx), %xmm0
|
|
pinsrw $6, %eax, %xmm0
|
|
shrl $16, %eax ;; EAX = 0 again!
|
|
pinsrw $7, %eax, %xmm0
|
|
movaps %xmm0, (%ecx)
|
|
ret
|
|
|
|
It would be better to generate:
|
|
|
|
_test:
|
|
movl 8(%esp), %ecx
|
|
movaps (%ecx), %xmm0
|
|
xor %eax, %eax
|
|
pinsrw $6, %eax, %xmm0
|
|
pinsrw $7, %eax, %xmm0
|
|
movaps %xmm0, (%ecx)
|
|
ret
|
|
|
|
or use pxor (to make a zero vector) and shuffle (to insert it).
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Some useful information in the Apple Altivec / SSE Migration Guide:
|
|
|
|
http://developer.apple.com/documentation/Performance/Conceptual/
|
|
Accelerate_sse_migration/index.html
|
|
|
|
e.g. SSE select using and, andnot, or. Various SSE compare translations.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Add hooks to commute some CMPP operations.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Implement some missing insert/extract element operations without going through
|
|
the stack. Testcase here:
|
|
CodeGen/X86/vec_ins_extract.ll
|
|
corresponds to this C code:
|
|
|
|
typedef float vectorfloat __attribute__((vector_size(16)));
|
|
void test(vectorfloat *F, float f) {
|
|
vectorfloat G = *F + *F;
|
|
*((float*)&G) = f;
|
|
*F = G + G;
|
|
}
|
|
void test2(vectorfloat *F, float f) {
|
|
vectorfloat G = *F + *F;
|
|
((float*)&G)[2] = f;
|
|
*F = G + G;
|
|
}
|
|
void test3(vectorfloat *F, float *f) {
|
|
vectorfloat G = *F + *F;
|
|
*f = ((float*)&G)[2];
|
|
}
|
|
void test4(vectorfloat *F, float *f) {
|
|
vectorfloat G = *F + *F;
|
|
*f = *((float*)&G);
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Apply the same transformation that merged four float into a single 128-bit load
|
|
to loads from constant pool.
|