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dc9a43dec1
This implements execute-only support for ARM code generation, which prevents the compiler from generating data accesses to code sections. The following changes are involved: * Add the CodeGen option "-arm-execute-only" to the ARM code generator. * Add the clang flag "-mexecute-only" as well as the GCC-compatible alias "-mpure-code" to enable this option. * When enabled, literal pools are replaced with MOVW/MOVT instructions, with VMOV used in addition for floating-point literals. As the MOVT instruction is required, execute-only support is only available in Thumb mode for targets supporting ARMv8-M baseline or Thumb2. * Jump tables are placed in data sections when in execute-only mode. * The execute-only text section is assigned section ID 0, and is marked as unreadable with the SHF_ARM_PURECODE flag with symbol 'y'. This also overrides selection of ELF sections for globals. llvm-svn: 289784
47 lines
1.9 KiB
LLVM
47 lines
1.9 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7m -arm-execute-only -O0 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
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; RUN: llc < %s -mtriple=thumbv8m.base -arm-execute-only -O0 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
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; RUN: llc < %s -mtriple=thumbv8m.main -arm-execute-only -O0 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
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define i8 @test_big_stack_frame() {
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; CHECK-SUBW-ADDW-LABEL: test_big_stack_frame:
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; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-SUBW-ADDW: sub.w sp, sp, #65536
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; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-SUBW-ADDW: add.w [[REG1:r[0-9]+]], sp, #255
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; CHECK-SUBW-ADDW: add.w {{r[0-9]+}}, [[REG1]], #65280
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; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-SUBW-ADDW: add.w lr, sp, #61440
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; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-SUBW-ADDW: add.w sp, sp, #65536
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; CHECK-MOVW-MOVT-ADD-LABEL: test_big_stack_frame:
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; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-MOVW-MOVT-ADD: movw [[REG1:r[0-9]+]], #0
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; CHECK-MOVW-MOVT-ADD: movt [[REG1]], #65535
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; CHECK-MOVW-MOVT-ADD: add sp, [[REG1]]
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; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-MOVW-MOVT-ADD: movw [[REG2:r[0-9]+]], #65532
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; CHECK-MOVW-MOVT-ADD: movt [[REG2]], #0
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; CHECK-MOVW-MOVT-ADD: add [[REG2]], sp
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; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-MOVW-MOVT-ADD: movw [[REG3:r[0-9]+]], #65532
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; CHECK-MOVW-MOVT-ADD: movt [[REG3]], #0
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; CHECK-MOVW-MOVT-ADD: add [[REG3]], sp
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; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-MOVW-MOVT-ADD: movw [[REG4:r[0-9]+]], #0
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; CHECK-MOVW-MOVT-ADD: movt [[REG4]], #1
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; CHECK-MOVW-MOVT-ADD: add sp, [[REG4]]
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entry:
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%s1 = alloca i8
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%buffer = alloca [65528 x i8], align 1
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call void @foo(i8* %s1)
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%load = load i8, i8* %s1
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ret i8 %load
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}
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declare void @foo(i8*)
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