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916e01c917
Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
157 lines
4.1 KiB
LLVM
157 lines
4.1 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 -disable-post-ra | FileCheck %s
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; RUN: llc < %s -march=arm -mattr=+vfp2 -disable-post-ra -regalloc=basic | FileCheck %s
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define void @test(float* %P, double* %D) {
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%A = load float* %P ; <float> [#uses=1]
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%B = load double* %D ; <double> [#uses=1]
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store float %A, float* %P
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store double %B, double* %D
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ret void
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}
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declare float @fabsf(float)
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declare double @fabs(double)
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define void @test_abs(float* %P, double* %D) {
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;CHECK: test_abs:
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%a = load float* %P ; <float> [#uses=1]
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;CHECK: vabs.f32
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%b = call float @fabsf( float %a ) ; <float> [#uses=1]
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store float %b, float* %P
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%A = load double* %D ; <double> [#uses=1]
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;CHECK: vabs.f64
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%B = call double @fabs( double %A ) ; <double> [#uses=1]
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store double %B, double* %D
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ret void
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}
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define void @test_add(float* %P, double* %D) {
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;CHECK: test_add:
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%a = load float* %P ; <float> [#uses=2]
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%b = fadd float %a, %a ; <float> [#uses=1]
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store float %b, float* %P
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%A = load double* %D ; <double> [#uses=2]
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%B = fadd double %A, %A ; <double> [#uses=1]
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store double %B, double* %D
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ret void
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}
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define void @test_ext_round(float* %P, double* %D) {
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;CHECK: test_ext_round:
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%a = load float* %P ; <float> [#uses=1]
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;CHECK: vcvt.f64.f32
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;CHECK: vcvt.f32.f64
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%b = fpext float %a to double ; <double> [#uses=1]
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%A = load double* %D ; <double> [#uses=1]
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%B = fptrunc double %A to float ; <float> [#uses=1]
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store double %b, double* %D
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store float %B, float* %P
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ret void
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}
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define void @test_fma(float* %P1, float* %P2, float* %P3) {
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;CHECK: test_fma:
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%a1 = load float* %P1 ; <float> [#uses=1]
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%a2 = load float* %P2 ; <float> [#uses=1]
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%a3 = load float* %P3 ; <float> [#uses=1]
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;CHECK: vnmls.f32
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%X = fmul float %a1, %a2 ; <float> [#uses=1]
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%Y = fsub float %X, %a3 ; <float> [#uses=1]
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store float %Y, float* %P1
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ret void
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}
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define i32 @test_ftoi(float* %P1) {
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;CHECK: test_ftoi:
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%a1 = load float* %P1 ; <float> [#uses=1]
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;CHECK: vcvt.s32.f32
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%b1 = fptosi float %a1 to i32 ; <i32> [#uses=1]
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ret i32 %b1
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}
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define i32 @test_ftou(float* %P1) {
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;CHECK: test_ftou:
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%a1 = load float* %P1 ; <float> [#uses=1]
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;CHECK: vcvt.u32.f32
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%b1 = fptoui float %a1 to i32 ; <i32> [#uses=1]
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ret i32 %b1
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}
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define i32 @test_dtoi(double* %P1) {
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;CHECK: test_dtoi:
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%a1 = load double* %P1 ; <double> [#uses=1]
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;CHECK: vcvt.s32.f64
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%b1 = fptosi double %a1 to i32 ; <i32> [#uses=1]
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ret i32 %b1
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}
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define i32 @test_dtou(double* %P1) {
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;CHECK: test_dtou:
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%a1 = load double* %P1 ; <double> [#uses=1]
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;CHECK: vcvt.u32.f64
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%b1 = fptoui double %a1 to i32 ; <i32> [#uses=1]
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ret i32 %b1
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}
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define void @test_utod(double* %P1, i32 %X) {
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;CHECK: test_utod:
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;CHECK: vcvt.f64.u32
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%b1 = uitofp i32 %X to double ; <double> [#uses=1]
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store double %b1, double* %P1
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ret void
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}
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define void @test_utod2(double* %P1, i8 %X) {
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;CHECK: test_utod2:
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;CHECK: vcvt.f64.u32
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%b1 = uitofp i8 %X to double ; <double> [#uses=1]
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store double %b1, double* %P1
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ret void
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}
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define void @test_cmp(float* %glob, i32 %X) {
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;CHECK: test_cmp:
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entry:
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%tmp = load float* %glob ; <float> [#uses=2]
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%tmp3 = getelementptr float* %glob, i32 2 ; <float*> [#uses=1]
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%tmp4 = load float* %tmp3 ; <float> [#uses=2]
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%tmp.upgrd.1 = fcmp oeq float %tmp, %tmp4 ; <i1> [#uses=1]
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%tmp5 = fcmp uno float %tmp, %tmp4 ; <i1> [#uses=1]
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%tmp6 = or i1 %tmp.upgrd.1, %tmp5 ; <i1> [#uses=1]
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;CHECK: bmi
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;CHECK-NEXT: bgt
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br i1 %tmp6, label %cond_true, label %cond_false
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cond_true: ; preds = %entry
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%tmp.upgrd.2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
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ret void
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cond_false: ; preds = %entry
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%tmp7 = tail call i32 (...)* @baz( ) ; <i32> [#uses=0]
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ret void
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}
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declare i1 @llvm.isunordered.f32(float, float)
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declare i32 @bar(...)
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declare i32 @baz(...)
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define void @test_cmpfp0(float* %glob, i32 %X) {
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;CHECK: test_cmpfp0:
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entry:
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%tmp = load float* %glob ; <float> [#uses=1]
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;CHECK: vcmpe.f32
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%tmp.upgrd.3 = fcmp ogt float %tmp, 0.000000e+00 ; <i1> [#uses=1]
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br i1 %tmp.upgrd.3, label %cond_true, label %cond_false
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cond_true: ; preds = %entry
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%tmp.upgrd.4 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
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ret void
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cond_false: ; preds = %entry
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%tmp1 = tail call i32 (...)* @baz( ) ; <i32> [#uses=0]
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ret void
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}
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