mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 18:54:02 +01:00
f5d3346387
For IR generated by a compiler, this is really simple: you just take the datalayout from the beginning of the file, and apply it to all the IR later in the file. For optimization testcases that don't care about the datalayout, this is also really simple: we just use the default datalayout. The complexity here comes from the fact that some LLVM tools allow overriding the datalayout: some tools have an explicit flag for this, some tools will infer a datalayout based on the code generation target. Supporting this properly required plumbing through a bunch of new machinery: we want to allow overriding the datalayout after the datalayout is parsed from the file, but before we use any information from it. Therefore, IR/bitcode parsing now has a callback to allow tools to compute the datalayout at the appropriate time. Not sure if I covered all the LLVM tools that want to use the callback. (clang? lli? Misc IR manipulation tools like llvm-link?). But this is at least enough for all the LLVM regression tests, and IR without a datalayout is not something frontends should generate. This change had some sort of weird effects for certain CodeGen regression tests: if the datalayout is overridden with a datalayout with a different program or stack address space, we now parse IR based on the overridden datalayout, instead of the one written in the file (or the default one, if none is specified). This broke a few AVR tests, and one AMDGPU test. Outside the CodeGen tests I mentioned, the test changes are all just fixing CHECK lines and moving around datalayout lines in weird places. Differential Revision: https://reviews.llvm.org/D78403
154 lines
4.8 KiB
LLVM
154 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
|
; RUN: opt -disable-output -print-mustexecute %s 2>&1 | FileCheck %s
|
|
|
|
define i1 @header_with_icf(i32* noalias %p, i32 %high) {
|
|
; CHECK-LABEL: @header_with_icf(
|
|
; CHECK-LABEL: loop:
|
|
; CHECK: %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] ; (mustexec in: loop)
|
|
; CHECK: %v = load i32, i32* %p, align 4 ; (mustexec in: loop)
|
|
; CHECK: call void @maythrow_and_use(i32 %v) ; (mustexec in: loop)
|
|
; CHECK-NOT: mustexec
|
|
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i32 [0, %entry], [%iv.next, %loop]
|
|
%v = load i32, i32* %p
|
|
call void @maythrow_and_use(i32 %v)
|
|
%iv.next = add nsw nuw i32 %iv, 1
|
|
%exit.test = icmp slt i32 %iv, %high
|
|
br i1 %exit.test, label %exit, label %loop
|
|
|
|
exit:
|
|
ret i1 false
|
|
}
|
|
|
|
define i1 @split_header(i32* noalias %p, i32 %high) {
|
|
; CHECK-LABEL: @split_header(
|
|
; CHECK-LABEL: loop:
|
|
; CHECK: %iv = phi i32 [ 0, %entry ], [ %iv.next, %next ] ; (mustexec in: loop)
|
|
; CHECK: %v = load i32, i32* %p, align 4 ; (mustexec in: loop)
|
|
; CHECK: br label %next ; (mustexec in: loop)
|
|
; CHECK-NOT: mustexec
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i32 [0, %entry], [%iv.next, %next]
|
|
%v = load i32, i32* %p
|
|
br label %next
|
|
next:
|
|
call void @maythrow_and_use(i32 %v)
|
|
%iv.next = add nsw nuw i32 %iv, 1
|
|
%exit.test = icmp slt i32 %iv, %high
|
|
br i1 %exit.test, label %exit, label %loop
|
|
|
|
exit:
|
|
ret i1 false
|
|
}
|
|
|
|
; FIXME: everything in inner loop header should be must execute
|
|
; for outer as well
|
|
define i1 @nested(i32* noalias %p, i32 %high) {
|
|
; CHECK-LABEL: @nested
|
|
; CHECK-LABEL: loop: ; preds = %next
|
|
; CHECK: %iv = phi i32 [ 0, %entry ], [ %iv.next, %next ] ; (mustexec in: loop)
|
|
; CHECK: br label %inner_loop ; (mustexec in: loop)
|
|
; CHECK-LABEL: inner_loop:
|
|
; CHECK: %v = load i32, i32* %p, align 4 ; (mustexec in: inner_loop)
|
|
; CHECK: %inner.test = icmp eq i32 %v, 0 ; (mustexec in: inner_loop)
|
|
; CHECK: br i1 %inner.test, label %inner_loop, label %next ; (mustexec in: inner_loop)
|
|
; CHECK-NOT: mustexec
|
|
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i32 [0, %entry], [%iv.next, %next]
|
|
br label %inner_loop
|
|
|
|
inner_loop:
|
|
%v = load i32, i32* %p
|
|
%inner.test = icmp eq i32 %v, 0
|
|
br i1 %inner.test, label %inner_loop, label %next
|
|
|
|
next:
|
|
call void @maythrow_and_use(i32 %v)
|
|
%iv.next = add nsw nuw i32 %iv, 1
|
|
%exit.test = icmp slt i32 %iv, %high
|
|
br i1 %exit.test, label %exit, label %loop
|
|
|
|
exit:
|
|
ret i1 false
|
|
}
|
|
|
|
define i1 @nested_no_throw(i32* noalias %p, i32 %high) {
|
|
; CHECK-LABEL: @nested_no_throw
|
|
; CHECK-LABEL: loop: ; preds = %next
|
|
; CHECK: %iv = phi i32 [ 0, %entry ], [ %iv.next, %next ] ; (mustexec in: loop)
|
|
; CHECK: br label %inner_loop ; (mustexec in: loop)
|
|
; CHECK-LABEL: inner_loop:
|
|
; CHECK: %v = load i32, i32* %p, align 4 ; (mustexec in 2 loops: inner_loop, loop)
|
|
; CHECK: %inner.test = icmp eq i32 %v, 0 ; (mustexec in 2 loops: inner_loop, loop)
|
|
; CHECK: br i1 %inner.test, label %inner_loop, label %next ; (mustexec in 2 loops: inner_loop, loop)
|
|
; CHECK-LABEL: next:
|
|
; CHECK: %iv.next = add nuw nsw i32 %iv, 1 ; (mustexec in: loop)
|
|
; CHECK: %exit.test = icmp slt i32 %iv, %high ; (mustexec in: loop)
|
|
; CHECK: br i1 %exit.test, label %exit, label %loop ; (mustexec in: loop)
|
|
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i32 [0, %entry], [%iv.next, %next]
|
|
br label %inner_loop
|
|
|
|
inner_loop:
|
|
%v = load i32, i32* %p
|
|
%inner.test = icmp eq i32 %v, 0
|
|
br i1 %inner.test, label %inner_loop, label %next
|
|
|
|
next:
|
|
%iv.next = add nsw nuw i32 %iv, 1
|
|
%exit.test = icmp slt i32 %iv, %high
|
|
br i1 %exit.test, label %exit, label %loop
|
|
|
|
exit:
|
|
ret i1 false
|
|
}
|
|
|
|
; Since all the instructions in the loop dominate the only exit
|
|
; and there's no implicit control flow in the loop, all must execute
|
|
; FIXME: handled by loop safety info, test it
|
|
define i1 @nothrow_loop(i32* noalias %p, i32 %high) {
|
|
; CHECK-LABEL: @nothrow_loop(
|
|
; CHECK-LABEL: loop:
|
|
; CHECK: %iv = phi i32 [ 0, %entry ], [ %iv.next, %next ] ; (mustexec in: loop)
|
|
; CHECK: br label %next ; (mustexec in: loop)
|
|
; CHECK-LABEL: next:
|
|
; CHECK: %v = load i32, i32* %p, align 4 ; (mustexec in: loop)
|
|
; CHECK: %iv.next = add nuw nsw i32 %iv, 1 ; (mustexec in: loop)
|
|
; CHECK: %exit.test = icmp slt i32 %iv, %high ; (mustexec in: loop)
|
|
; CHECK: br i1 %exit.test, label %exit, label %loop ; (mustexec in: loop)
|
|
; CHECK-NOT: mustexec
|
|
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i32 [0, %entry], [%iv.next, %next]
|
|
br label %next
|
|
next:
|
|
%v = load i32, i32* %p
|
|
%iv.next = add nsw nuw i32 %iv, 1
|
|
%exit.test = icmp slt i32 %iv, %high
|
|
br i1 %exit.test, label %exit, label %loop
|
|
|
|
exit:
|
|
ret i1 false
|
|
}
|
|
|
|
|
|
declare void @maythrow_and_use(i32)
|