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2567a1faf7
%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
19 lines
522 B
ArmAsm
19 lines
522 B
ArmAsm
# RUN: not llvm-mc -triple riscv32 -filetype obj < %s -o /dev/null 2>&1 | FileCheck %s
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jal a0, far_distant # CHECK: :[[@LINE]]:3: error: fixup value out of range
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jal a0, unaligned # CHECK: :[[@LINE]]:3: error: fixup value must be 2-byte aligned
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beq a0, a1, distant # CHECK: :[[@LINE]]:3: error: fixup value out of range
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blt t0, t1, unaligned # CHECK: :[[@LINE]]:3: error: fixup value must be 2-byte aligned
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.byte 0
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unaligned:
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.byte 0
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.byte 0
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.byte 0
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.space 1<<12
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distant:
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.space 1<<20
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far_distant:
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