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39932105f0
This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
10 lines
534 B
ArmAsm
10 lines
534 B
ArmAsm
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbt < %s 2>&1 | FileCheck %s
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# Too few operands
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fslw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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# Too few operands
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fsrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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# Immediate operand out of range
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fsriw t0, t1, t2, 32 # CHECK: :[[@LINE]]:19: error: immediate must be an integer in the range [0, 31]
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fsriw t0, t1, t2, -1 # CHECK: :[[@LINE]]:19: error: immediate must be an integer in the range [0, 31]
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