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90cca807df
This matters for byval uses outside of the entry block, which appear as copies. Previously, the only folding done was during selection, which could not see the underlying frame index. For any uses outside the entry block, the frame index was materialized in the entry block relative to the global scratch wave offset. This may produce worse code in cases where the offset ends up not fitting in the MUBUF offset field. A better heuristic would be helpfu for extreme frames. llvm-svn: 364185
74 lines
2.7 KiB
LLVM
74 lines
2.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
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declare i32 @llvm.amdgcn.readfirstlane(i32) #0
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; CHECK-LABEL: {{^}}test_readfirstlane:
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; CHECK: v_readfirstlane_b32 s{{[0-9]+}}, v2
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define void @test_readfirstlane(i32 addrspace(1)* %out, i32 %src) #1 {
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%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %src)
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store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_readfirstlane_imm:
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; CHECK: s_mov_b32 [[SGPR_VAL:s[0-9]]], 32
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; CHECK-NOT: [[SGPR_VAL]]
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; CHECK: ; use [[SGPR_VAL]]
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define amdgpu_kernel void @test_readfirstlane_imm(i32 addrspace(1)* %out) #1 {
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%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 32)
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call void asm sideeffect "; use $0", "s"(i32 %readfirstlane)
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ret void
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}
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; CHECK-LABEL: {{^}}test_readfirstlane_imm_fold:
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; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], 32
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; CHECK-NOT: [[VVAL]]
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]
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define amdgpu_kernel void @test_readfirstlane_imm_fold(i32 addrspace(1)* %out) #1 {
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%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 32)
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store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; TODO: m0 should be folded.
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; CHECK-LABEL: {{^}}test_readfirstlane_m0:
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; CHECK: s_mov_b32 m0, -1
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; CHECK: s_mov_b32 [[COPY_M0:s[0-9]+]], m0
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; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], [[COPY_M0]]
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]
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define amdgpu_kernel void @test_readfirstlane_m0(i32 addrspace(1)* %out) #1 {
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%m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()
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%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %m0)
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store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_readfirstlane_copy_from_sgpr:
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; CHECK: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 [[SGPR:s[0-9]+]]
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; CHECK: ;;#ASMEND
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; CHECK-NOT: [[SGPR]]
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; CHECK-NOT: readfirstlane
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; CHECK: v_mov_b32_e32 [[VCOPY:v[0-9]+]], [[SGPR]]
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VCOPY]]
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define amdgpu_kernel void @test_readfirstlane_copy_from_sgpr(i32 addrspace(1)* %out) #1 {
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%sgpr = call i32 asm "s_mov_b32 $0, 0", "=s"()
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%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %sgpr)
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store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; Make sure this doesn't crash.
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; CHECK-LABEL: {{^}}test_readfirstlane_fi:
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; CHECK: s_mov_b32 [[FIVAL:s[0-9]]], 4
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define amdgpu_kernel void @test_readfirstlane_fi(i32 addrspace(1)* %out) #1 {
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%alloca = alloca i32, addrspace(5)
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%int = ptrtoint i32 addrspace(5)* %alloca to i32
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%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %int)
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call void asm sideeffect "; use $0", "s"(i32 %readfirstlane)
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ret void
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}
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attributes #0 = { nounwind readnone convergent }
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attributes #1 = { nounwind }
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