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45f41f7ab1
This is a more general alternative/extension to D102635. Rather than handling the special case of "header exit with non-exiting latch", this unrolls against the smallest exact trip count from any exit. The latch exit is no longer treated as priviledged when it comes to full unrolling. The motivating case is in full-unroll-one-unpredictable-exit.ll. Here the header exit is an IV-based exit, while the latch exit is a data comparison. This kind of loop does not get rotated, because the latch is already exiting, and loop rotation doesn't try to distinguish IV-based/analyzable latches. Differential Revision: https://reviews.llvm.org/D102982
345 lines
13 KiB
LLVM
345 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -S -indvars -loop-unroll -verify-loop-info | FileCheck %s
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;
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; Unit tests for loop unrolling using ScalarEvolution to compute trip counts.
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;
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; Indvars is run first to generate an "old" SCEV result. Some unit
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; tests may check that SCEV is properly invalidated between passes.
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; Completely unroll loops without a canonical IV.
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define i32 @sansCanonical(i32* %base) nounwind {
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; CHECK-LABEL: @sansCanonical(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
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; CHECK: while.body:
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; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[BASE:%.*]], i64 9
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; CHECK-NEXT: [[TMP:%.*]] = load i32, i32* [[ADR]], align 8
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; CHECK-NEXT: [[ADR_1:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 8
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; CHECK-NEXT: [[TMP_1:%.*]] = load i32, i32* [[ADR_1]], align 8
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; CHECK-NEXT: [[SUM_NEXT_1:%.*]] = add i32 [[TMP]], [[TMP_1]]
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; CHECK-NEXT: [[ADR_2:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 7
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; CHECK-NEXT: [[TMP_2:%.*]] = load i32, i32* [[ADR_2]], align 8
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; CHECK-NEXT: [[SUM_NEXT_2:%.*]] = add i32 [[SUM_NEXT_1]], [[TMP_2]]
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; CHECK-NEXT: [[ADR_3:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 6
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; CHECK-NEXT: [[TMP_3:%.*]] = load i32, i32* [[ADR_3]], align 8
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; CHECK-NEXT: [[SUM_NEXT_3:%.*]] = add i32 [[SUM_NEXT_2]], [[TMP_3]]
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; CHECK-NEXT: [[ADR_4:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 5
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; CHECK-NEXT: [[TMP_4:%.*]] = load i32, i32* [[ADR_4]], align 8
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; CHECK-NEXT: [[SUM_NEXT_4:%.*]] = add i32 [[SUM_NEXT_3]], [[TMP_4]]
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; CHECK-NEXT: [[ADR_5:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 4
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; CHECK-NEXT: [[TMP_5:%.*]] = load i32, i32* [[ADR_5]], align 8
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; CHECK-NEXT: [[SUM_NEXT_5:%.*]] = add i32 [[SUM_NEXT_4]], [[TMP_5]]
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; CHECK-NEXT: [[ADR_6:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 3
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; CHECK-NEXT: [[TMP_6:%.*]] = load i32, i32* [[ADR_6]], align 8
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; CHECK-NEXT: [[SUM_NEXT_6:%.*]] = add i32 [[SUM_NEXT_5]], [[TMP_6]]
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; CHECK-NEXT: [[ADR_7:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 2
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; CHECK-NEXT: [[TMP_7:%.*]] = load i32, i32* [[ADR_7]], align 8
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; CHECK-NEXT: [[SUM_NEXT_7:%.*]] = add i32 [[SUM_NEXT_6]], [[TMP_7]]
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; CHECK-NEXT: [[ADR_8:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 1
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; CHECK-NEXT: [[TMP_8:%.*]] = load i32, i32* [[ADR_8]], align 8
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; CHECK-NEXT: [[SUM_NEXT_8:%.*]] = add i32 [[SUM_NEXT_7]], [[TMP_8]]
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; CHECK-NEXT: ret i32 [[SUM_NEXT_8]]
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;
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entry:
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br label %while.body
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while.body:
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%iv = phi i64 [ 10, %entry ], [ %iv.next, %while.body ]
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%sum = phi i32 [ 0, %entry ], [ %sum.next, %while.body ]
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%iv.next = add i64 %iv, -1
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%adr = getelementptr inbounds i32, i32* %base, i64 %iv.next
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%tmp = load i32, i32* %adr, align 8
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%sum.next = add i32 %sum, %tmp
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%iv.narrow = trunc i64 %iv.next to i32
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%cmp.i65 = icmp sgt i32 %iv.narrow, 0
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br i1 %cmp.i65, label %while.body, label %exit
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exit:
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ret i32 %sum
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}
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; SCEV unrolling properly handles loops with multiple exits. In this
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; case, the computed trip count based on a canonical IV is *not* for a
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; latch block.
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define i64 @earlyLoopTest(i64* %base) nounwind {
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; CHECK-LABEL: @earlyLoopTest(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[VAL:%.*]] = load i64, i64* [[BASE:%.*]], align 4
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; CHECK-NEXT: br label [[TAIL:%.*]]
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; CHECK: tail:
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i64 [[VAL]], 0
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; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP_1:%.*]], label [[EXIT2:%.*]]
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; CHECK: exit1:
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; CHECK-NEXT: [[S_LCSSA:%.*]] = phi i64 [ [[S_NEXT_2:%.*]], [[LOOP_3:%.*]] ]
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; CHECK-NEXT: ret i64 [[S_LCSSA]]
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; CHECK: exit2:
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; CHECK-NEXT: [[S_NEXT_LCSSA1:%.*]] = phi i64 [ [[VAL]], [[TAIL]] ], [ [[S_NEXT_1:%.*]], [[TAIL_1:%.*]] ], [ [[S_NEXT_2]], [[TAIL_2:%.*]] ], [ [[S_NEXT_3:%.*]], [[TAIL_3:%.*]] ]
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; CHECK-NEXT: ret i64 [[S_NEXT_LCSSA1]]
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; CHECK: loop.1:
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; CHECK-NEXT: [[ADR_1:%.*]] = getelementptr i64, i64* [[BASE]], i64 1
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; CHECK-NEXT: [[VAL_1:%.*]] = load i64, i64* [[ADR_1]], align 4
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; CHECK-NEXT: [[S_NEXT_1]] = add i64 [[VAL]], [[VAL_1]]
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; CHECK-NEXT: br label [[TAIL_1]]
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; CHECK: tail.1:
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; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ne i64 [[VAL_1]], 0
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; CHECK-NEXT: br i1 [[CMP2_1]], label [[LOOP_2:%.*]], label [[EXIT2]]
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; CHECK: loop.2:
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; CHECK-NEXT: [[ADR_2:%.*]] = getelementptr i64, i64* [[BASE]], i64 2
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; CHECK-NEXT: [[VAL_2:%.*]] = load i64, i64* [[ADR_2]], align 4
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; CHECK-NEXT: [[S_NEXT_2]] = add i64 [[S_NEXT_1]], [[VAL_2]]
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; CHECK-NEXT: br label [[TAIL_2]]
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; CHECK: tail.2:
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; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ne i64 [[VAL_2]], 0
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; CHECK-NEXT: br i1 [[CMP2_2]], label [[LOOP_3]], label [[EXIT2]]
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; CHECK: loop.3:
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; CHECK-NEXT: [[ADR_3:%.*]] = getelementptr i64, i64* [[BASE]], i64 3
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; CHECK-NEXT: [[VAL_3:%.*]] = load i64, i64* [[ADR_3]], align 4
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; CHECK-NEXT: [[S_NEXT_3]] = add i64 [[S_NEXT_2]], [[VAL_3]]
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; CHECK-NEXT: br i1 false, label [[TAIL_3]], label [[EXIT1:%.*]]
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; CHECK: tail.3:
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; CHECK-NEXT: br label [[EXIT2]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %inc, %tail ]
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%s = phi i64 [ 0, %entry ], [ %s.next, %tail ]
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%adr = getelementptr i64, i64* %base, i64 %iv
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%val = load i64, i64* %adr
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%s.next = add i64 %s, %val
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%inc = add i64 %iv, 1
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%cmp = icmp ne i64 %inc, 4
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br i1 %cmp, label %tail, label %exit1
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tail:
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%cmp2 = icmp ne i64 %val, 0
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br i1 %cmp2, label %loop, label %exit2
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exit1:
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ret i64 %s
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exit2:
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ret i64 %s.next
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}
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; SCEV properly unrolls multi-exit loops.
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define i32 @multiExit(i32* %base) nounwind {
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; CHECK-LABEL: @multiExit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[L1:%.*]]
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; CHECK: l1:
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; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[BASE:%.*]], align 4
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; CHECK-NEXT: br i1 false, label [[L2:%.*]], label [[EXIT1:%.*]]
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; CHECK: l2:
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; CHECK-NEXT: ret i32 [[VAL]]
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; CHECK: exit1:
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; CHECK-NEXT: ret i32 1
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;
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entry:
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br label %l1
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l1:
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%iv1 = phi i32 [ 0, %entry ], [ %inc1, %l2 ]
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%iv2 = phi i32 [ 0, %entry ], [ %inc2, %l2 ]
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%inc1 = add i32 %iv1, 1
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%inc2 = add i32 %iv2, 1
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%adr = getelementptr i32, i32* %base, i32 %iv1
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%val = load i32, i32* %adr
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%cmp1 = icmp slt i32 %iv1, 5
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br i1 %cmp1, label %l2, label %exit1
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l2:
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%cmp2 = icmp slt i32 %iv2, 10
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br i1 %cmp2, label %l1, label %exit2
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exit1:
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ret i32 1
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exit2:
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ret i32 %val
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}
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; SCEV can unroll a multi-exit loops even if the latch block has no
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; known trip count, but an early exit has a known trip count. In this
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; case we must be careful not to optimize the latch branch away.
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define i32 @multiExitIncomplete(i32* %base) nounwind {
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; CHECK-LABEL: @multiExitIncomplete(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[L1:%.*]]
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; CHECK: l1:
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; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[BASE:%.*]], align 4
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; CHECK-NEXT: br label [[L2:%.*]]
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; CHECK: l2:
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; CHECK-NEXT: br label [[L3:%.*]]
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; CHECK: l3:
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; CHECK-NEXT: [[CMP3:%.*]] = icmp ne i32 [[VAL]], 0
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; CHECK-NEXT: br i1 [[CMP3]], label [[L1_1:%.*]], label [[EXIT3:%.*]]
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; CHECK: exit1:
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; CHECK-NEXT: ret i32 1
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; CHECK: exit2:
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; CHECK-NEXT: ret i32 2
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; CHECK: exit3:
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; CHECK-NEXT: ret i32 3
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; CHECK: l1.1:
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; CHECK-NEXT: [[ADR_1:%.*]] = getelementptr i32, i32* [[BASE]], i32 1
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; CHECK-NEXT: [[VAL_1:%.*]] = load i32, i32* [[ADR_1]], align 4
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; CHECK-NEXT: br label [[L2_1:%.*]]
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; CHECK: l2.1:
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; CHECK-NEXT: br label [[L3_1:%.*]]
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; CHECK: l3.1:
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; CHECK-NEXT: [[CMP3_1:%.*]] = icmp ne i32 [[VAL_1]], 0
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; CHECK-NEXT: br i1 [[CMP3_1]], label [[L1_2:%.*]], label [[EXIT3]]
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; CHECK: l1.2:
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; CHECK-NEXT: [[ADR_2:%.*]] = getelementptr i32, i32* [[BASE]], i32 2
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; CHECK-NEXT: [[VAL_2:%.*]] = load i32, i32* [[ADR_2]], align 4
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; CHECK-NEXT: br label [[L2_2:%.*]]
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; CHECK: l2.2:
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; CHECK-NEXT: br label [[L3_2:%.*]]
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; CHECK: l3.2:
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; CHECK-NEXT: [[CMP3_2:%.*]] = icmp ne i32 [[VAL_2]], 0
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; CHECK-NEXT: br i1 [[CMP3_2]], label [[L1_3:%.*]], label [[EXIT3]]
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; CHECK: l1.3:
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; CHECK-NEXT: [[ADR_3:%.*]] = getelementptr i32, i32* [[BASE]], i32 3
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; CHECK-NEXT: [[VAL_3:%.*]] = load i32, i32* [[ADR_3]], align 4
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; CHECK-NEXT: br label [[L2_3:%.*]]
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; CHECK: l2.3:
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; CHECK-NEXT: br label [[L3_3:%.*]]
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; CHECK: l3.3:
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; CHECK-NEXT: [[CMP3_3:%.*]] = icmp ne i32 [[VAL_3]], 0
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; CHECK-NEXT: br i1 [[CMP3_3]], label [[L1_4:%.*]], label [[EXIT3]]
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; CHECK: l1.4:
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; CHECK-NEXT: [[ADR_4:%.*]] = getelementptr i32, i32* [[BASE]], i32 4
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; CHECK-NEXT: [[VAL_4:%.*]] = load i32, i32* [[ADR_4]], align 4
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; CHECK-NEXT: br label [[L2_4:%.*]]
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; CHECK: l2.4:
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; CHECK-NEXT: br label [[L3_4:%.*]]
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; CHECK: l3.4:
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; CHECK-NEXT: [[CMP3_4:%.*]] = icmp ne i32 [[VAL_4]], 0
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; CHECK-NEXT: br i1 [[CMP3_4]], label [[L1_5:%.*]], label [[EXIT3]]
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; CHECK: l1.5:
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; CHECK-NEXT: br i1 false, label [[L2_5:%.*]], label [[EXIT1:%.*]]
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; CHECK: l2.5:
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; CHECK-NEXT: br i1 true, label [[L3_5:%.*]], label [[EXIT2:%.*]]
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; CHECK: l3.5:
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; CHECK-NEXT: br label [[EXIT3]]
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;
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entry:
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br label %l1
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l1:
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%iv1 = phi i32 [ 0, %entry ], [ %inc1, %l3 ]
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%iv2 = phi i32 [ 0, %entry ], [ %inc2, %l3 ]
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%inc1 = add i32 %iv1, 1
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%inc2 = add i32 %iv2, 1
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%adr = getelementptr i32, i32* %base, i32 %iv1
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%val = load i32, i32* %adr
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%cmp1 = icmp slt i32 %iv1, 5
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br i1 %cmp1, label %l2, label %exit1
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l2:
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%cmp2 = icmp slt i32 %iv2, 10
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br i1 %cmp2, label %l3, label %exit2
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l3:
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%cmp3 = icmp ne i32 %val, 0
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br i1 %cmp3, label %l1, label %exit3
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exit1:
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ret i32 1
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exit2:
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ret i32 2
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exit3:
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ret i32 3
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}
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; When loop unroll merges a loop exit with one of its parent loop's
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; exits, SCEV must forget its ExitNotTaken info.
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define void @nestedUnroll() nounwind {
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; CHECK-LABEL: @nestedUnroll(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_INC:%.*]]
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; CHECK: for.inc:
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; CHECK-NEXT: br label [[FOR_BODY38:%.*]]
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; CHECK: for.body38:
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; CHECK-NEXT: br label [[FOR_BODY43:%.*]]
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; CHECK: for.body43:
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; CHECK-NEXT: br label [[FOR_BODY87:%.*]]
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; CHECK: for.body87:
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; CHECK-NEXT: br label [[FOR_BODY87]]
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;
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entry:
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br label %for.inc
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for.inc:
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br i1 false, label %for.inc, label %for.body38.preheader
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for.body38.preheader:
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br label %for.body38
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for.body38:
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%i.113 = phi i32 [ %inc76, %for.inc74 ], [ 0, %for.body38.preheader ]
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%mul48 = mul nsw i32 %i.113, 6
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br label %for.body43
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for.body43:
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%j.011 = phi i32 [ 0, %for.body38 ], [ %inc72, %for.body43 ]
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%add49 = add nsw i32 %j.011, %mul48
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%sh_prom50 = zext i32 %add49 to i64
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%inc72 = add nsw i32 %j.011, 1
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br i1 false, label %for.body43, label %for.inc74
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for.inc74:
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%inc76 = add nsw i32 %i.113, 1
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br i1 false, label %for.body38, label %for.body87.preheader
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for.body87.preheader:
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br label %for.body87
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for.body87:
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br label %for.body87
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}
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; PR16130: clang produces incorrect code with loop/expression at -O2
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; rdar:14036816 loop-unroll makes assumptions about undefined behavior
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;
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; The loop latch is assumed to exit after the first iteration because
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; of the induction variable's NSW flag. However, the loop latch's
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; equality test is skipped and the loop exits after the second
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; iteration via the early exit. So loop unrolling cannot assume that
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; the loop latch's exit count of zero is an upper bound on the number
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; of iterations.
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define void @nsw_latch(i32* %a) nounwind {
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; CHECK-LABEL: @nsw_latch(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: br label [[FOR_COND:%.*]]
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; CHECK: for.cond:
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; CHECK-NEXT: br i1 false, label [[RETURN:%.*]], label [[FOR_BODY_1:%.*]]
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; CHECK: return:
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; CHECK-NEXT: [[B_03_LCSSA:%.*]] = phi i32 [ 0, [[FOR_COND]] ], [ 8, [[FOR_BODY_1]] ], [ 0, [[FOR_COND_1:%.*]] ]
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; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[FOR_COND]] ], [ 1, [[FOR_BODY_1]] ], [ 0, [[FOR_COND_1]] ]
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; CHECK-NEXT: store i32 [[B_03_LCSSA]], i32* [[A:%.*]], align 4
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; CHECK-NEXT: ret void
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; CHECK: for.body.1:
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; CHECK-NEXT: br i1 false, label [[FOR_COND_1]], label [[RETURN]]
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; CHECK: for.cond.1:
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; CHECK-NEXT: br label [[RETURN]]
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;
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entry:
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br label %for.body
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for.body: ; preds = %for.cond, %entry
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%b.03 = phi i32 [ 0, %entry ], [ %add, %for.cond ]
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%tobool = icmp eq i32 %b.03, 0
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%add = add nsw i32 %b.03, 8
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br i1 %tobool, label %for.cond, label %return
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for.cond: ; preds = %for.body
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%cmp = icmp eq i32 %add, 13
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br i1 %cmp, label %return, label %for.body
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return: ; preds = %for.body, %for.cond
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%b.03.lcssa = phi i32 [ %b.03, %for.body ], [ %b.03, %for.cond ]
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%retval.0 = phi i32 [ 1, %for.body ], [ 0, %for.cond ]
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store i32 %b.03.lcssa, i32* %a, align 4
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ret void
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}
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