David Green 4637cdfdf0 [AArch64] Set the latency of Cortex-A55 stores to 1 ... This sets the latency of stores to 1 in the Cortex-A55 scheduling model, to better match the values given in the software optimization guide. The latency of a store in normal llvm scheduling does not appear to have a lot of uses. If the store has no outputs then the latency is somewhat meaningless (and pre/post increment update operands use the WriteAdr write for those operands instead). The one place it does alter things is the latency between a store and the end of the scheduling region, which can in turn have an effect on the critical path length. As a result a latency of 1 is more correct and offers ever-so-slightly better scheduling of instructions near the end of the block. They are marked as RetireOOO to keep the llvm-mca from introducing stalls where non would exist. Differential Revision: https://reviews.llvm.org/D105541		2021-07-12 13:39:35 +01:00
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AArch64	[AArch64] Set the latency of Cortex-A55 stores to 1	2021-07-12 13:39:35 +01:00
AMDGPU	Revert "[MCA] [AMDGPU] Adding an implementation to AMDGPUCustomBehaviour for handling s_waitcnt instructions."	2021-07-07 20:48:42 -07:00
ARM	[MCA][InstrBuilder] Check for the presence of flag VariadicOpsAreDefs.	2021-06-15 09:52:38 +01:00
JSON/X86	[llvm-mca][JSON] Teach the PipelinePrinter how to deal with anonymous code regions (PR51008)	2021-07-10 13:57:52 +01:00
SystemZ
X86	[X86][Atom] Fix vector fp<->int resource/throughputs	2021-07-07 16:52:34 +01:00
invalid_input_file_name.test	[test] Use host platform specific error message substitution in lit tests	2021-01-29 07:16:30 -05:00
lit.local.cfg