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84 lines
3.6 KiB
TableGen
84 lines
3.6 KiB
TableGen
//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target-independent scheduling interfaces which should
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// be implemented by each target which is using TableGen based scheduling.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Processor functional unit - These values represent the function units
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// available across all chip sets for the target. Eg., IntUnit, FPUnit, ...
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// These may be independent values for each chip set or may be shared across
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// all chip sets of the target. Each functional unit is treated as a resource
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// during scheduling and has an affect instruction order based on availability
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// during a time interval.
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//
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class FuncUnit;
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//===----------------------------------------------------------------------===//
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// Instruction stage - These values represent a non-pipelined step in
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// the execution of an instruction. Cycles represents the number of
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// discrete time slots needed to complete the stage. Units represent
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// the choice of functional units that can be used to complete the
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// stage. Eg. IntUnit1, IntUnit2. NextCycles indicates how many
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// cycles should elapse from the start of this stage to the start of
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// the next stage in the itinerary. For example:
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//
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// A stage is specified in one of two ways:
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//
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// InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles
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// InstrStage<1, [FU_x, FU_y], 0> - TimeInc explicit
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//
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class InstrStage<int cycles, list<FuncUnit> units, int timeinc = -1> {
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int Cycles = cycles; // length of stage in machine cycles
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list<FuncUnit> Units = units; // choice of functional units
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int TimeInc = timeinc; // cycles till start of next stage
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}
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//===----------------------------------------------------------------------===//
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// Instruction itinerary - An itinerary represents a sequential series of steps
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// required to complete an instruction. Itineraries are represented as lists of
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// instruction stages.
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//
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//===----------------------------------------------------------------------===//
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// Instruction itinerary classes - These values represent 'named' instruction
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// itinerary. Using named itineraries simplifies managing groups of
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// instructions across chip sets. An instruction uses the same itinerary class
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// across all chip sets. Thus a new chip set can be added without modifying
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// instruction information.
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//
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class InstrItinClass;
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def NoItinerary : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Instruction itinerary data - These values provide a runtime map of an
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// instruction itinerary class (name) to its itinerary data.
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//
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class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
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list<int> operandcycles = []> {
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InstrItinClass TheClass = Class;
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list<InstrStage> Stages = stages;
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list<int> OperandCycles = operandcycles;
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}
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//===----------------------------------------------------------------------===//
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// Processor itineraries - These values represent the set of all itinerary
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// classes for a given chip set.
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//
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class ProcessorItineraries<list<InstrItinData> iid> {
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list<InstrItinData> IID = iid;
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}
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// NoItineraries - A marker that can be used by processors without schedule
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// info.
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def NoItineraries : ProcessorItineraries<[]>;
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