Kristof Beyls d33917748d Make ARMAsmParser accept the correct alignment specifier syntax in instructions. ... The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] llvm-svn: 175164		2013-02-14 14:46:12 +00:00
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AArch64	Implement external weak (ELF) symbols on AArch64	2013-02-06 16:43:33 +00:00
ARM	Make ARMAsmParser accept the correct alignment specifier syntax in instructions.	2013-02-14 14:46:12 +00:00
CPP
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon	Hexagon: add support for predicate-GPR copies.	2013-02-13 22:56:34 +00:00
MBlaze
Mips	For Mips 16, add the optimization where the 16 bit form of addiu sp can be used	2013-02-13 20:28:27 +00:00
MSP430
NVPTX	[NVPTX] Disable vector registers	2013-02-12 14:18:49 +00:00
PowerPC	DAGCombiner: Constant folding around pre-increment loads/stores	2013-02-08 21:35:47 +00:00
R600	R600: Add lit tests for texture sampling instruction selection.	2013-02-14 07:43:51 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC
Thumb	Use the 'count' attribute to calculate the upper bound of an array.	2012-12-04 21:34:03 +00:00
Thumb2	FileCheck-ify some grep tests	2013-01-25 22:11:46 +00:00
X86	Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).	2013-02-14 08:20:26 +00:00
XCore