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d886da55a2
Simplify 'shl' inequality test into 'and' equality test. This pattern happens in the middle-end while simplifying bitfield access, Exposed in https://reviews.llvm.org/D63505 https://rise4fun.com/Alive/6uz Reviewers: lebedev.ri, efriedma Reviewed By: lebedev.ri Subscribers: spatel, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63675 llvm-svn: 364348
116 lines
3.8 KiB
LLVM
116 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; With left shift, the comparison should not be modified.
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define i1 @test_shift_and_cmp_not_changed1(i8 %p) {
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; CHECK-LABEL: @test_shift_and_cmp_not_changed1(
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; CHECK-NEXT: [[SHLP:%.*]] = shl i8 [[P:%.*]], 5
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; CHECK-NEXT: [[ANDP:%.*]] = and i8 [[SHLP]], -64
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%shlp = shl i8 %p, 5
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%andp = and i8 %shlp, -64
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%cmp = icmp slt i8 %andp, 32
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ret i1 %cmp
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}
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; With arithmetic right shift, the comparison should not be modified.
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define i1 @test_shift_and_cmp_not_changed2(i8 %p) {
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; CHECK-LABEL: @test_shift_and_cmp_not_changed2(
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; CHECK-NEXT: [[SHLP:%.*]] = ashr i8 [[P:%.*]], 5
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; CHECK-NEXT: [[ANDP:%.*]] = and i8 [[SHLP]], -64
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%shlp = ashr i8 %p, 5
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%andp = and i8 %shlp, -64
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%cmp = icmp slt i8 %andp, 32
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ret i1 %cmp
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}
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; This should simplify functionally to the left shift case.
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; The extra input parameter should be optimized away.
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define i1 @test_shift_and_cmp_changed1(i8 %p, i8 %q) {
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; CHECK-LABEL: @test_shift_and_cmp_changed1(
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; CHECK-NEXT: [[ANDP:%.*]] = shl i8 [[P:%.*]], 5
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; CHECK-NEXT: [[SHL:%.*]] = and i8 [[ANDP]], -64
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[SHL]], 32
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%andp = and i8 %p, 6
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%andq = and i8 %q, 8
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%or = or i8 %andq, %andp
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%shl = shl i8 %or, 5
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%ashr = ashr i8 %shl, 5
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%cmp = icmp slt i8 %ashr, 1
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ret i1 %cmp
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}
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define <2 x i1> @test_shift_and_cmp_changed1_vec(<2 x i8> %p, <2 x i8> %q) {
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; CHECK-LABEL: @test_shift_and_cmp_changed1_vec(
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; CHECK-NEXT: [[ANDP:%.*]] = shl <2 x i8> [[P:%.*]], <i8 5, i8 5>
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; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[ANDP]], <i8 -64, i8 -64>
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[SHL]], <i8 32, i8 32>
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%andp = and <2 x i8> %p, <i8 6, i8 6>
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%andq = and <2 x i8> %q, <i8 8, i8 8>
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%or = or <2 x i8> %andq, %andp
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%shl = shl <2 x i8> %or, <i8 5, i8 5>
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%ashr = ashr <2 x i8> %shl, <i8 5, i8 5>
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%cmp = icmp slt <2 x i8> %ashr, <i8 1, i8 1>
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ret <2 x i1> %cmp
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}
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; Unsigned compare allows a transformation to compare against 0.
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define i1 @test_shift_and_cmp_changed2(i8 %p) {
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; CHECK-LABEL: @test_shift_and_cmp_changed2(
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; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[P:%.*]], 6
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%shlp = shl i8 %p, 5
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%andp = and i8 %shlp, -64
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%cmp = icmp ult i8 %andp, 32
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ret i1 %cmp
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}
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define <2 x i1> @test_shift_and_cmp_changed2_vec(<2 x i8> %p) {
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; CHECK-LABEL: @test_shift_and_cmp_changed2_vec(
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; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[P:%.*]], <i8 6, i8 6>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[TMP1]], zeroinitializer
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%shlp = shl <2 x i8> %p, <i8 5, i8 5>
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%andp = and <2 x i8> %shlp, <i8 -64, i8 -64>
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%cmp = icmp ult <2 x i8> %andp, <i8 32, i8 32>
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ret <2 x i1> %cmp
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}
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; nsw on the shift should not affect the comparison.
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define i1 @test_shift_and_cmp_changed3(i8 %p) {
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; CHECK-LABEL: @test_shift_and_cmp_changed3(
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; CHECK-NEXT: [[SHLP:%.*]] = shl nsw i8 [[P:%.*]], 5
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; CHECK-NEXT: [[ANDP:%.*]] = and i8 [[SHLP]], -64
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%shlp = shl nsw i8 %p, 5
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%andp = and i8 %shlp, -64
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%cmp = icmp slt i8 %andp, 32
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ret i1 %cmp
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}
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; Logical shift right allows a return true because the 'and' guarantees no bits are set.
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define i1 @test_shift_and_cmp_changed4(i8 %p) {
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; CHECK-LABEL: @test_shift_and_cmp_changed4(
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; CHECK-NEXT: ret i1 true
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;
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%shlp = lshr i8 %p, 5
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%andp = and i8 %shlp, -64
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%cmp = icmp slt i8 %andp, 32
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ret i1 %cmp
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}
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