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llvm-mirror/test/MC/Disassembler/ARM/invalid-SRS-arm.txt
Johnny Chen 785ab1531b Fix SRS/SRSW encoding bits.
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS

Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.

llvm-svn: 128864
2011-04-05 00:16:18 +00:00

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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=0 Name=PHI Format=(42)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1|
# -------------------------------------------------------------------------------------------------
# Unknown format
#
# B6.1.10 SRS
# Inst{19-8} = 0xd05
# Inst{7-5} = 0b000
0x83 0x1c 0xc5 0xf8