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llvm-mirror/test/CodeGen
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Simon Pilgrim 5f8f0b3a1b [X86][SSE] Add target shuffle support to X86TargetLowering::computeKnownBitsForTargetNode 
Ideally we'd use resolveTargetShuffleInputs to handle faux shuffles as well but:
(a) that code path doesn't handle general/pre-legalized ops/types very well.
(b) I'm concerned about the compute time as they recurse to calls to computeKnownBits/ComputeNumSignBits which would need depth limiting somehow.

llvm-svn: 334007
2018-06-05 10:52:29 +00:00
..
AArch64 [ShrinkWrap] Add optimization remarks to the shrink-wrapping pass 2018-06-05 00:27:24 +00:00
AMDGPU [CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperands 2018-06-04 20:19:45 +00:00
ARC
ARM [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part) 2018-06-02 16:40:03 +00:00
AVR
BPF [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
Generic [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
Hexagon [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZ 2018-06-01 14:52:58 +00:00
Inputs
Lanai Remove SETCCE use from Lanai's backend 2018-06-03 12:56:24 +00:00
Mips [mips] Restore the availablity of trap for microMIPS 2018-06-04 12:50:32 +00:00
MIR [MIRParser] Add parser support for 'true' and 'false' i1s. 2018-06-05 00:17:13 +00:00
MSP430 Emit a left-shift instead of a power-of-two multiply for jump-tables 2018-05-16 08:58:26 +00:00
Nios2
NVPTX [DAG] fold FP binops with undef operands to NaN 2018-05-21 23:54:19 +00:00
PowerPC [PowerPC] Fix the incorrect iterator inside peephole 2018-05-29 13:38:56 +00:00
RISCV [RISCV] Add peepholes for Global Address lowering patterns 2018-05-29 19:34:54 +00:00
SPARC [Sparc] Select correct register class for FP register constraints 2018-05-30 06:07:55 +00:00
SystemZ [SystemZ] Bugfix in combineSTORE(). 2018-05-25 09:01:23 +00:00
Thumb
Thumb2 [Thumb2] fix typo in test from r332548 2018-05-17 03:24:25 +00:00
WebAssembly [WebAssembly] Update to the new names for the memory intrinsics. 2018-05-31 22:35:25 +00:00
WinCFGuard
WinEH [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
X86 [X86][SSE] Add target shuffle support to X86TargetLowering::computeKnownBitsForTargetNode 2018-06-05 10:52:29 +00:00
XCore [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00