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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
llvm-mirror/test/TableGen
Daniel Sanders 5bcb5b930a [globalisel][tablegen] Fix an multi-insn match bug where ComplexPattern is used on multiple insns.
In each rule, each use of ComplexPattern is assigned an element in the Renderers
array. The matcher then collects renderer functions in this array and they are
used to render instructions. This works well for a single instruction but a
bug in the allocation mechanism causes the elements to be assigned on a
per-instruction basis rather than a per-rule basis.

So in the case of:
  (set GPR32:$dst, (Op complex:$src1, complex:$src2))
tablegen currently assigns elements 0 and 1 to $src1 and $src2 respectively,
but for:
  (set GPR32:$dst, (Op complex:$src1, (Op complex:$src2)))
it currently assigned both $src1 and $src2 the same element (0). This results in
one complex operand being rendered twice and the other being forgotten.
This patch corrects the allocation such that $src1 and $src2 are still allocated
different elements in this case.

llvm-svn: 307646
2017-07-11 10:40:18 +00:00
..
2003-08-03-PassCode.td
2006-09-18-LargeInt.td
2010-03-24-PrematureDefaults.td
AnonDefinitionOnDemand.td
AsmPredicateCondsEmission.td
AsmVariant.td [TableGen] Add a proper namespace to an Instruction in an AsmMatcher test. This is required after r307358. 2017-07-07 05:50:45 +00:00
BitOffsetDecoder.td
BitsInit.td
BitsInitOverflow.td
cast-list-initializer.td
cast.td
ClassInstanceValue.td
CStyleComment.td
Dag.td
defmclass.td
DefmInherit.td
DefmInsideMultiClass.td
DuplicateFieldValues.td
eq.td
eqbit.td
FieldAccess.td
foreach.td
ForeachList.td
ForeachLoop.td
ForwardRef.td
GeneralList.td
GlobalISelEmitter.td [globalisel][tablegen] Fix an multi-insn match bug where ComplexPattern is used on multiple insns. 2017-07-11 10:40:18 +00:00
if-empty-list-arg.td
if.td
ifbit.td
Include.inc
Include.td
IntBitInit.td
intrinsic-long-name.td [MVT][SVE] Scalable vector MVTs (2/3) 2017-04-20 13:36:58 +00:00
intrinsic-varargs.td [MVT] add v1i1 MVT 2017-05-18 11:29:41 +00:00
LazyChange.td
LetInsideMultiClasses.td
lisp.td
list-element-bitref.td
ListArgs.td
ListArgsSimple.td
listconcat.td
ListConversion.td
ListManip.td
ListOfList.td
ListSlices.td
lit.local.cfg
LoLoL.td
math.td
MultiClass.td
MultiClassDefName.td
MultiClassInherit.td
MultiPat.td
nested-comment.td
NestedForeach.td
Paste.td
pr8330.td
RegisterBankEmitter.td
RegisterEncoder.td [TableGen] Add EncoderMethod to RegisterOperand 2017-05-15 10:13:07 +00:00
SetTheory.td
SiblingForeach.td
Slice.td
strconcat.td
String.td
subst2.td
subst.td
SuperSubclassSameName.td
TargetInstrInfo.td
TargetInstrSpec.td
TemplateArgRename.td
Tree.td
TreeNames.td
trydecode-emission2.td
trydecode-emission3.td
trydecode-emission.td
TwoLevelName.td
UnsetBitInit.td
UnterminatedComment.td
usevalname.td
ValidIdentifiers.td