Chuang-Yu Cheng d389efdf8e [ppc64] fix bug in prologue that mfocrf's cr operand should be explict state instead of implicit ... This fixes PR27414 Reviewers: kbarton mgrang tjablin http://reviews.llvm.org/D19255 llvm-svn: 267660		2016-04-27 02:59:28 +00:00
..
AArch64	[AArch64] Expand v1i64 and v2i64 ctlz.	2016-04-26 05:26:51 +00:00
AMDGPU	[AMDGPU] Reserve VGPRs for trap handler usage if instructed	2016-04-26 15:43:14 +00:00
ARM	[ARM] Expand vector ctlz_zero_undef so it becomes ctlz.	2016-04-26 05:04:37 +00:00
BPF
CPP
Generic	Introduce llvm.load.relative intrinsic.	2016-04-22 21:18:02 +00:00
Hexagon	[Tail duplication] Handle source registers with subregisters	2016-04-26 18:36:34 +00:00
Inputs
Lanai	[lanai] Add subword scheduling itineraries.	2016-04-20 18:28:55 +00:00
Mips	[mips][microMIPS] Revert commit r267137	2016-04-25 15:40:08 +00:00
MIR	tests: tweak MIR for ARM tests to correct MI issues	2016-04-26 17:54:21 +00:00
MSP430
NVPTX
PowerPC	[ppc64] fix bug in prologue that mfocrf's cr operand should be explict state instead of implicit	2016-04-27 02:59:28 +00:00
SPARC	[SPARC] [SSP] Add support for LOAD_STACK_GUARD.	2016-04-26 10:37:14 +00:00
SystemZ	[SystemZ] [SSP] Add support for LOAD_STACK_GUARD.	2016-04-24 13:57:49 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Account for implicit operands when computing operand indices.	2016-04-26 01:40:56 +00:00
WinEH
X86	[X86] Don't assume that MMX extractelts are from index 0.	2016-04-27 01:35:29 +00:00
XCore