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llvm-mirror/test/CodeGen/AArch64/madd-combiner.ll
Juergen Ributzka af69801c85 Reapply r216805 "[MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR.""
This reapplies r216805 with a fix to a copy-past error, which resulted in an
incorrect register class.

Original commit message:
Select the correct register class for the various instructions that are
generated when combining instructions and constrain the registers to the
appropriate register class.

This fixes rdar://problem/18183707.

llvm-svn: 217019
2014-09-03 07:07:10 +00:00

21 lines
580 B
LLVM

; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; Test that we use the correct register class.
define i32 @mul_add_imm(i32 %a, i32 %b) {
; CHECK-LABEL: mul_add_imm
; CHECK: orr [[REG:w[0-9]+]], wzr, #0x4
; CHECK-NEXT: madd {{w[0-9]+}}, w0, w1, [[REG]]
%1 = mul i32 %a, %b
%2 = add i32 %1, 4
ret i32 %2
}
define i32 @mul_sub_imm1(i32 %a, i32 %b) {
; CHECK-LABEL: mul_sub_imm1
; CHECK: orr [[REG:w[0-9]+]], wzr, #0x4
; CHECK-NEXT: msub {{w[0-9]+}}, w0, w1, [[REG]]
%1 = mul i32 %a, %b
%2 = sub i32 4, %1
ret i32 %2
}