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llvm-mirror/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll
Matt Arsenault 304779755d AMDGPU: Add cache invalidation instructions.
These are necessary for implementing mem_fence for
OpenCL 2.0.

The VI assembler tests are disabled since it seems to be
using the wrong encoding or opcode.

llvm-svn: 248532
2015-09-24 19:52:21 +00:00

15 lines
438 B
LLVM

; RUN: llc -march=amdgcn -mcpu=tahiti -show-mc-encoding < %s | FileCheck -check-prefix=SI %s
declare void @llvm.amdgcn.buffer.wbinvl1.sc() #0
; SI-LABEL: {{^}}test_buffer_wbinvl1_sc:
; SI-NEXT: ; BB#0:
; SI-NEXT: buffer_wbinvl1_sc ; encoding: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00]
; SI-NEXT: s_endpgm
define void @test_buffer_wbinvl1_sc() #0 {
call void @llvm.amdgcn.buffer.wbinvl1.sc()
ret void
}
attributes #0 = { nounwind }