1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 20:12:56 +02:00
llvm-mirror/test/CodeGen/ARM/wide-compares.ll
Peter Collingbourne dcf4c81cd2 ARM: Better codegen for 64-bit compares.
This introduces a custom lowering for ISD::SETCCE (introduced in r253572)
that allows us to emit a short code sequence for 64-bit compares.

Before:

	push	{r7, lr}
	cmp	r0, r2
	mov.w	r0, #0
	mov.w	r12, #0
	it	hs
	movhs	r0, #1
	cmp	r1, r3
	it	ge
	movge.w	r12, #1
	it	eq
	moveq	r12, r0
	cmp.w	r12, #0
	bne	.LBB1_2
@ BB#1:                                 @ %bb1
	bl	f
	pop	{r7, pc}
.LBB1_2:                                @ %bb2
	bl	g
	pop	{r7, pc}

After:

	push	{r7, lr}
	subs	r0, r0, r2
	sbcs.w	r0, r1, r3
	bge	.LBB1_2
@ BB#1:                                 @ %bb1
	bl	f
	pop	{r7, pc}
.LBB1_2:                                @ %bb2
	bl	g
	pop	{r7, pc}

Saves around 80KB in Chromium's libchrome.so.

Some notes on this patch:

- I don't much like the ARMISD::BRCOND and ARMISD::CMOV combines I
  introduced (nothing else needs them). However, they are necessary in
  order to avoid poor codegen, and they seem similar to existing combines
  in other backends (e.g. X86 combines (brcond (cmp (setcc Compare))) to
  (brcond Compare)).

- No support for Thumb-1. This is in principle possible, but we'd need
  to implement ARMISD::SUBE for Thumb-1.

Differential Revision: http://reviews.llvm.org/D15256

llvm-svn: 263962
2016-03-21 18:00:02 +00:00

53 lines
1.4 KiB
LLVM

; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM %s
; RUN: llc -mtriple=thumbv6-unknown-linux < %s | FileCheck --check-prefix=CHECK-THUMB1 %s
; RUN: llc -mtriple=thumbv7-unknown-linux < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-THUMB2 %s
; CHECK-THUMB1-NOT: sbc
; CHECK-LABEL: test_slt1:
define i32 @test_slt1(i64 %a, i64 %b) {
entry:
; CHECK-ARM: subs {{[^,]+}}, r0, r2
; CHECK-ARM: mov [[TMP:[0-9a-z]+]], #2
; CHECK-ARM: sbcs {{[^,]+}}, r1, r3
; CHECK-ARM: movwlt [[TMP]], #1
; CHECK-ARM: mov r0, [[TMP]]
; CHECK-ARM: bx lr
; CHECK-THUMB2: subs {{[^,]+}}, r0, r2
; CHECK-THUMB2: mov.w [[TMP:[0-9a-z]+]], #2
; CHECK-THUMB2: sbcs.w {{[^,]+}}, r1, r3
; CHECK-THUMB2: it lt
; CHECK-THUMB2: movlt.w [[TMP]], #1
; CHECK-THUMB2: mov r0, [[TMP]]
; CHECK-THUMB2: bx lr
%cmp = icmp slt i64 %a, %b
br i1 %cmp, label %bb1, label %bb2
bb1:
ret i32 1
bb2:
ret i32 2
}
; CHECK-LABEL: test_slt2:
define void @test_slt2(i64 %a, i64 %b) {
entry:
%cmp = icmp slt i64 %a, %b
; CHECK-ARM: subs {{[^,]+}}, r0, r2
; CHECK-ARM: sbcs {{[^,]+}}, r1, r3
; CHECK-THUMB2: subs {{[^,]+}}, r0, r2
; CHECK-THUMB2: sbcs.w {{[^,]+}}, r1, r3
; CHECK: bge [[BB2:\.[0-9A-Za-z_]+]]
br i1 %cmp, label %bb1, label %bb2
bb1:
call void @f()
ret void
bb2:
; CHECK: [[BB2]]:
; CHECK-NEXT: bl g
call void @g()
ret void
}
declare void @f()
declare void @g()