Kai Luo adf785206e [PowerPC] Export 16 byte load-store instructions ... Export `lq`, `stq`, `lqarx` and `stqcx.` in preparation for implementing 16-byte lock free atomic operations on AIX. Add a new register class `g8prc` for these instructions, since these instructions require even-odd register pair. Reviewed By: nemanjai, jsji, #powerpc Differential Revision: https://reviews.llvm.org/D103010		2021-06-15 01:56:10 +00:00
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cfi-register-directive-parse.s
dcbt.s
deprecated-p7.s
directive-parse-err.s
htm.s
invalid-instructions-spellcheck.s
lcomm.s
lit.local.cfg
modern-aix-as.s
p10.s
pcrel-tls-general-dynamic-address-load-reloc.s
pcrel-tls-general-dynamic-value-load-reloc.s
pcrel-tls-initial-exec-address-load-reloc.s
pcrel-tls-initial-exec-value-load-reloc.s
pcrel-tls-local-dynamic-reloc.s
pcrel-tls-local-exec-address-load-reloc.s
pcrel-tls-local-exec-value-load-reloc.s
ppc32-ba.s
ppc32-extpid-e500.s
ppc32-reloc-directive.s
ppc64-abiversion.s
ppc64-dq-expr.s
ppc64-encoding-4xx.s
ppc64-encoding-6xx.s
ppc64-encoding-bookII.s
ppc64-encoding-bookIII.s
ppc64-encoding-e500.s
ppc64-encoding-ext.s
ppc64-encoding-fp.s
ppc64-encoding-ISA31-errors.s
ppc64-encoding-ISA31-pcrel-reloc.s
ppc64-encoding-ISA31.s
ppc64-encoding-p8vector.s
ppc64-encoding-spe.s
ppc64-encoding-vmx.s
ppc64-encoding.s
ppc64-errors-emit-obj.s
ppc64-errors.s
ppc64-fixup-apply.s
ppc64-fixup-explicit.s
ppc64-fixups.s
ppc64-initial-cfa.s
ppc64-localentry-error1.s
ppc64-localentry-error2.s
ppc64-localentry-symbols.s
ppc64-localentry.s
ppc64-operands.s
ppc64-prefix-align-labels.s
ppc64-prefix-align.s
ppc64-regs.s
ppc64-reloc-directive-pcrel.s
ppc64-reloc-directive.s
ppc64-relocs-01.s
ppc64-tls-relocs-01.s
ppc-llong.s
ppc-machine.s
ppc-nop.s
ppc-reloc.s
ppc-word.s
pr24686.s
pr38945.s
st-other-crash.s
tls-gd-obj.s
tls-ie-obj.s
tls-ld-obj.s
tls-ld-v2-abi.s
tls-le-v2-abi.s
vsx.s