Guozhi Wei 37cf363f24 [PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0 ... According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0. This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified. Differential Revision: https://reviews.llvm.org/D32880 llvm-svn: 302834		2017-05-11 22:17:35 +00:00
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AArch64	[AArch64] armv8-A doesn't have CRC.	2017-05-03 20:33:52 +00:00
AMDGPU	AMDGPU: Remove tfe bit from flat instruction definitions	2017-05-11 17:38:33 +00:00
ARM	[ARM] Clear the constant pool cache on explicit .ltorg directives	2017-05-08 10:26:24 +00:00
AsmParser	[LLVM][inline-asm] Altmacro string escape character '!'	2017-05-10 13:08:11 +00:00
AVR	[AVR] Fix a bug so that we now emit R_AVR_16 fixups with the correct offset	2017-04-30 23:33:52 +00:00
COFF	MC/COFF: Do not emit forward associative section referenceds.	2017-02-17 17:32:54 +00:00
Disassembler	[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0	2017-05-11 22:17:35 +00:00
ELF	Add llvm::object::getELFSectionTypeName().	2017-05-02 14:04:52 +00:00
Hexagon	[Hexagon] Change iconst to emit 27bit relocation	2017-05-02 18:19:11 +00:00
Lanai
MachO	MCMacho: Allow __thread_ptr section after dwarf sections	2017-02-01 01:31:36 +00:00
Markup
Mips	[mips] Emit R_MICROMIPS_TLS_GOTTPREL relocation for %gottprel in case of microMIPS	2017-04-30 04:27:23 +00:00
PowerPC	[PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic	2017-03-15 16:04:53 +00:00
Sparc
SystemZ	[SystemZ] Add miscellaneous instructions	2017-05-10 14:20:15 +00:00
WebAssembly	[WebAssembly] Add size of section header to data relocation offsets.	2017-04-28 21:22:38 +00:00
X86	[X86][LWP] Add llvm support for LWP instructions (reapplied).	2017-05-03 15:51:39 +00:00