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2f96de340f
Lay some groundwork for converting to MC-based asm printer. This is the first of probably many patches to bring the back-end back up-to-date with all of the recent MC changes. llvm-svn: 140697
355 lines
10 KiB
C++
355 lines
10 KiB
C++
//===-- PTXISelDAGToDAG.cpp - A dag to dag inst selector for PTX ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the PTX target.
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//
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//===----------------------------------------------------------------------===//
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#include "PTX.h"
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#include "PTXMachineFunctionInfo.h"
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#include "PTXTargetMachine.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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// PTXDAGToDAGISel - PTX specific code to select PTX machine
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// instructions for SelectionDAG operations.
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class PTXDAGToDAGISel : public SelectionDAGISel {
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public:
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PTXDAGToDAGISel(PTXTargetMachine &TM, CodeGenOpt::Level OptLevel);
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virtual const char *getPassName() const {
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return "PTX DAG->DAG Pattern Instruction Selection";
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}
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SDNode *Select(SDNode *Node);
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// Complex Pattern Selectors.
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bool SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2);
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bool SelectADDRri(SDValue &Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRii(SDValue &Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRlocal(SDValue &Addr, SDValue &Base, SDValue &Offset);
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// Include the pieces auto'gened from the target description
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#include "PTXGenDAGISel.inc"
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private:
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// We need this only because we can't match intruction BRAdp
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// pattern (PTXbrcond bb:$d, ...) in PTXInstrInfo.td
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SDNode *SelectBRCOND(SDNode *Node);
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SDNode *SelectREADPARAM(SDNode *Node);
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SDNode *SelectWRITEPARAM(SDNode *Node);
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SDNode *SelectFrameIndex(SDNode *Node);
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bool isImm(const SDValue &operand);
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bool SelectImm(const SDValue &operand, SDValue &imm);
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const PTXSubtarget& getSubtarget() const;
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}; // class PTXDAGToDAGISel
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} // namespace
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// createPTXISelDag - This pass converts a legalized DAG into a
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// PTX-specific DAG, ready for instruction scheduling
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FunctionPass *llvm::createPTXISelDag(PTXTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new PTXDAGToDAGISel(TM, OptLevel);
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}
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PTXDAGToDAGISel::PTXDAGToDAGISel(PTXTargetMachine &TM,
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CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel) {}
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SDNode *PTXDAGToDAGISel::Select(SDNode *Node) {
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switch (Node->getOpcode()) {
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case ISD::BRCOND:
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return SelectBRCOND(Node);
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case PTXISD::READ_PARAM:
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return SelectREADPARAM(Node);
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case PTXISD::WRITE_PARAM:
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return SelectWRITEPARAM(Node);
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case ISD::FrameIndex:
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return SelectFrameIndex(Node);
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default:
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return SelectCode(Node);
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}
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}
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SDNode *PTXDAGToDAGISel::SelectBRCOND(SDNode *Node) {
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assert(Node->getNumOperands() >= 3);
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SDValue Chain = Node->getOperand(0);
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SDValue Pred = Node->getOperand(1);
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SDValue Target = Node->getOperand(2); // branch target
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SDValue PredOp = CurDAG->getTargetConstant(PTX::PRED_NORMAL, MVT::i32);
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DebugLoc dl = Node->getDebugLoc();
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assert(Target.getOpcode() == ISD::BasicBlock);
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assert(Pred.getValueType() == MVT::i1);
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// Emit BRAdp
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SDValue Ops[] = { Target, Pred, PredOp, Chain };
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return CurDAG->getMachineNode(PTX::BRAdp, dl, MVT::Other, Ops, 4);
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}
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SDNode *PTXDAGToDAGISel::SelectREADPARAM(SDNode *Node) {
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SDValue Chain = Node->getOperand(0);
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SDValue Index = Node->getOperand(1);
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int OpCode;
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// Get the type of parameter we are reading
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EVT VT = Node->getValueType(0);
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assert(VT.isSimple() && "READ_PARAM only implemented for MVT types");
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MVT Type = VT.getSimpleVT();
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if (Type == MVT::i1)
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OpCode = PTX::READPARAMPRED;
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else if (Type == MVT::i16)
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OpCode = PTX::READPARAMI16;
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else if (Type == MVT::i32)
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OpCode = PTX::READPARAMI32;
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else if (Type == MVT::i64)
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OpCode = PTX::READPARAMI64;
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else if (Type == MVT::f32)
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OpCode = PTX::READPARAMF32;
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else if (Type == MVT::f64)
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OpCode = PTX::READPARAMF64;
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SDValue Pred = CurDAG->getRegister(PTX::NoRegister, MVT::i1);
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SDValue PredOp = CurDAG->getTargetConstant(PTX::PRED_NONE, MVT::i32);
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DebugLoc dl = Node->getDebugLoc();
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SDValue Ops[] = { Index, Pred, PredOp, Chain };
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return CurDAG->getMachineNode(OpCode, dl, VT, Ops, 4);
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}
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SDNode *PTXDAGToDAGISel::SelectWRITEPARAM(SDNode *Node) {
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SDValue Chain = Node->getOperand(0);
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SDValue Value = Node->getOperand(1);
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int OpCode;
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//Node->dumpr(CurDAG);
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// Get the type of parameter we are writing
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EVT VT = Value->getValueType(0);
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assert(VT.isSimple() && "WRITE_PARAM only implemented for MVT types");
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MVT Type = VT.getSimpleVT();
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if (Type == MVT::i1)
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OpCode = PTX::WRITEPARAMPRED;
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else if (Type == MVT::i16)
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OpCode = PTX::WRITEPARAMI16;
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else if (Type == MVT::i32)
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OpCode = PTX::WRITEPARAMI32;
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else if (Type == MVT::i64)
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OpCode = PTX::WRITEPARAMI64;
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else if (Type == MVT::f32)
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OpCode = PTX::WRITEPARAMF32;
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else if (Type == MVT::f64)
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OpCode = PTX::WRITEPARAMF64;
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else
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llvm_unreachable("Invalid type in SelectWRITEPARAM");
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SDValue Pred = CurDAG->getRegister(PTX::NoRegister, MVT::i1);
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SDValue PredOp = CurDAG->getTargetConstant(PTX::PRED_NONE, MVT::i32);
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DebugLoc dl = Node->getDebugLoc();
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SDValue Ops[] = { Value, Pred, PredOp, Chain };
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SDNode* Ret = CurDAG->getMachineNode(OpCode, dl, MVT::Other, Ops, 4);
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//dbgs() << "SelectWRITEPARAM produced:\n\t";
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//Ret->dumpr(CurDAG);
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return Ret;
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}
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SDNode *PTXDAGToDAGISel::SelectFrameIndex(SDNode *Node) {
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int FI = cast<FrameIndexSDNode>(Node)->getIndex();
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//dbgs() << "Selecting FrameIndex at index " << FI << "\n";
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//SDValue TFI = CurDAG->getTargetFrameIndex(FI, Node->getValueType(0));
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PTXMachineFunctionInfo *MFI = MF->getInfo<PTXMachineFunctionInfo>();
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SDValue FrameSymbol = CurDAG->getTargetExternalSymbol(MFI->getFrameSymbol(FI),
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Node->getValueType(0));
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return FrameSymbol.getNode();
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}
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// Match memory operand of the form [reg+reg]
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bool PTXDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2) {
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if (Addr.getOpcode() != ISD::ADD || Addr.getNumOperands() < 2 ||
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isImm(Addr.getOperand(0)) || isImm(Addr.getOperand(1)))
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return false;
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assert(Addr.getValueType().isSimple() && "Type must be simple");
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
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return true;
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}
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// Match memory operand of the form [reg], [imm+reg], and [reg+imm]
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bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base,
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SDValue &Offset) {
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// FrameIndex addresses are handled separately
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//errs() << "SelectADDRri: ";
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//Addr.getNode()->dumpr();
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if (isa<FrameIndexSDNode>(Addr)) {
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//errs() << "Failure\n";
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return false;
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}
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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Base = Addr.getOperand(0);
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if (isa<FrameIndexSDNode>(Base)) {
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//errs() << "Failure\n";
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return false;
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}
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
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//errs() << "Success\n";
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return true;
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}
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/*if (Addr.getNumOperands() == 1) {
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
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errs() << "Success\n";
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return true;
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}*/
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//errs() << "SelectADDRri fails on: ";
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//Addr.getNode()->dumpr();
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if (isImm(Addr)) {
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//errs() << "Failure\n";
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return false;
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
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//errs() << "Success\n";
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return true;
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/*if (Addr.getOpcode() != ISD::ADD) {
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// let SelectADDRii handle the [imm] case
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if (isImm(Addr))
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return false;
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// it is [reg]
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assert(Addr.getValueType().isSimple() && "Type must be simple");
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
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return true;
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}
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if (Addr.getNumOperands() < 2)
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return false;
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// let SelectADDRii handle the [imm+imm] case
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if (isImm(Addr.getOperand(0)) && isImm(Addr.getOperand(1)))
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return false;
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// try [reg+imm] and [imm+reg]
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for (int i = 0; i < 2; i ++)
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if (SelectImm(Addr.getOperand(1-i), Offset)) {
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Base = Addr.getOperand(i);
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return true;
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}
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// neither [reg+imm] nor [imm+reg]
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return false;*/
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}
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// Match memory operand of the form [imm+imm] and [imm]
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bool PTXDAGToDAGISel::SelectADDRii(SDValue &Addr, SDValue &Base,
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SDValue &Offset) {
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// is [imm+imm]?
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if (Addr.getOpcode() == ISD::ADD) {
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return SelectImm(Addr.getOperand(0), Base) &&
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SelectImm(Addr.getOperand(1), Offset);
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}
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// is [imm]?
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if (SelectImm(Addr, Base)) {
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assert(Addr.getValueType().isSimple() && "Type must be simple");
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Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
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return true;
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}
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return false;
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}
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// Match memory operand of the form [reg], [imm+reg], and [reg+imm]
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bool PTXDAGToDAGISel::SelectADDRlocal(SDValue &Addr, SDValue &Base,
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SDValue &Offset) {
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//errs() << "SelectADDRlocal: ";
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//Addr.getNode()->dumpr();
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if (isa<FrameIndexSDNode>(Addr)) {
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
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//errs() << "Success\n";
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return true;
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}
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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Base = Addr.getOperand(0);
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if (!isa<FrameIndexSDNode>(Base)) {
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//errs() << "Failure\n";
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return false;
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}
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
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//errs() << "Offset: ";
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//Offset.getNode()->dumpr();
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//errs() << "Success\n";
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return true;
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}
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//errs() << "Failure\n";
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return false;
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}
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bool PTXDAGToDAGISel::isImm(const SDValue &operand) {
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return ConstantSDNode::classof(operand.getNode());
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}
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bool PTXDAGToDAGISel::SelectImm(const SDValue &operand, SDValue &imm) {
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SDNode *node = operand.getNode();
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if (!ConstantSDNode::classof(node))
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return false;
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ConstantSDNode *CN = cast<ConstantSDNode>(node);
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imm = CurDAG->getTargetConstant(*CN->getConstantIntValue(),
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operand.getValueType());
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return true;
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}
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const PTXSubtarget& PTXDAGToDAGISel::getSubtarget() const
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{
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return TM.getSubtarget<PTXSubtarget>();
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}
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