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caef091029
This code seems to be target dependent which may not be the same for all targets. Passed the decision whether the given stride is complex or not to the target by sending stride information via SCEV to getAddressComputationCost instead of 'IsComplex'. Specifically at X86 targets we dont see any significant address computation cost in case of the strided access in general. Differential Revision: https://reviews.llvm.org/D27518 llvm-svn: 291106
140 lines
4.4 KiB
C++
140 lines
4.4 KiB
C++
//===-- AArch64TargetTransformInfo.h - AArch64 specific TTI -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// AArch64 target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
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#include "AArch64.h"
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#include "AArch64TargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/Target/TargetLowering.h"
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#include <algorithm>
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namespace llvm {
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class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
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typedef BasicTTIImplBase<AArch64TTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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friend BaseT;
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const AArch64Subtarget *ST;
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const AArch64TargetLowering *TLI;
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/// Estimate the overhead of scalarizing an instruction. Insert and Extract
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/// are set if the result needs to be inserted and/or extracted from vectors.
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unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
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const AArch64Subtarget *getST() const { return ST; }
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const AArch64TargetLowering *getTLI() const { return TLI; }
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enum MemIntrinsicType {
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VECTOR_LDST_TWO_ELEMENTS,
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VECTOR_LDST_THREE_ELEMENTS,
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VECTOR_LDST_FOUR_ELEMENTS
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};
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public:
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explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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/// \name Scalar TTI Implementations
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/// @{
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using BaseT::getIntImmCost;
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int getIntImmCost(int64_t Val);
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int getIntImmCost(const APInt &Imm, Type *Ty);
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int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
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int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty);
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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bool enableInterleavedAccessVectorization() { return true; }
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unsigned getNumberOfRegisters(bool Vector) {
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if (Vector) {
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if (ST->hasNEON())
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return 32;
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return 0;
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}
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return 31;
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}
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unsigned getRegisterBitWidth(bool Vector) {
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if (Vector) {
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if (ST->hasNEON())
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return 128;
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return 0;
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}
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return 64;
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}
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unsigned getMaxInterleaveFactor(unsigned VF);
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int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
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int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy,
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unsigned Index);
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int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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int getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
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int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr);
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int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
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int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace);
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int getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys);
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void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP);
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Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
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Type *ExpectedType);
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bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
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int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
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ArrayRef<unsigned> Indices, unsigned Alignment,
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unsigned AddressSpace);
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unsigned getCacheLineSize();
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unsigned getPrefetchDistance();
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unsigned getMinPrefetchStride();
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unsigned getMaxPrefetchIterationsAhead();
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/// @}
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};
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} // end namespace llvm
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#endif
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