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75eff6e3b0
Some instructions have a fixed Z register and don't have an explicit register operand. This can be worked around by simply printing the operand directly if the particular register class is detected. The LPM and ELPM instructions also needed a custom decoder, which is also included in this patch. Differential Revision: https://reviews.llvm.org/D82088
30 lines
700 B
ArmAsm
30 lines
700 B
ArmAsm
; RUN: llvm-mc -triple avr -mattr=elpm,elpmx -show-encoding < %s | FileCheck %s
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; RUN: llvm-mc -filetype=obj -triple avr -mattr=elpm,elpmx < %s | llvm-objdump -d --mattr=elpm,elpmx - | FileCheck -check-prefix=CHECK-INST %s
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foo:
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elpm
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elpm r3, Z
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elpm r23, Z
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elpm r8, Z+
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elpm r0, Z+
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; CHECK: elpm ; encoding: [0xd8,0x95]
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; CHECK: elpm r3, Z ; encoding: [0x36,0x90]
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; CHECK: elpm r23, Z ; encoding: [0x76,0x91]
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; CHECK: elpm r8, Z+ ; encoding: [0x87,0x90]
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; CHECK: elpm r0, Z+ ; encoding: [0x07,0x90]
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; CHECK-INST: elpm
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; CHECK-INST: elpm r3, Z
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; CHECK-INST: elpm r23, Z
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; CHECK-INST: elpm r8, Z+
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; CHECK-INST: elpm r0, Z+
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