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a2254d3fcc
If we need to shift left anyway we might be able to take advantage of LUI implicitly shifting its immediate left by 12 to cover part of the shift. This allows us to use more bits of the LUI immediate to avoid an ADDI. isDesirableToCommuteWithShift now considers compressed instruction opportunities when deciding if commuting should be allowed. I believe this is the same or similar to one of the optimizations from D79492. Reviewed By: luismarques, arcbbb Differential Revision: https://reviews.llvm.org/D105417
213 lines
5.8 KiB
ArmAsm
213 lines
5.8 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases \
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# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv64 \
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# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
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# RUN: | llvm-objdump -M no-aliases -d - \
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# RUN: | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-EXPAND,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
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# RUN: | llvm-objdump -d - \
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# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
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# The following check prefixes are used in this test:
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# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
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# CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
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# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
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# TODO ld
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# TODO sd
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# Needed for testing valid %pcrel_lo expressions
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.Lpcrel_hi0: auipc a0, %pcrel_hi(foo)
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# CHECK-INST: addi a0, zero, 0
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# CHECK-ALIAS: mv a0, zero
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li x10, 0
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# CHECK-EXPAND: addi a0, zero, 1
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li x10, 1
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# CHECK-EXPAND: addi a0, zero, -1
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li x10, -1
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# CHECK-EXPAND: addi a0, zero, 2047
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li x10, 2047
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# CHECK-EXPAND: addi a0, zero, -2047
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li x10, -2047
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# CHECK-EXPAND: lui a1, 1
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# CHECK-EXPAND: addiw a1, a1, -2048
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li x11, 2048
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# CHECK-EXPAND: addi a1, zero, -2048
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li x11, -2048
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# CHECK-EXPAND: lui a1, 1
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# CHECK-EXPAND: addiw a1, a1, -2047
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li x11, 2049
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# CHECK-EXPAND: lui a1, 1048575
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# CHECK-EXPAND: addiw a1, a1, 2047
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li x11, -2049
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# CHECK-EXPAND: lui a1, 1
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# CHECK-EXPAND: addiw a1, a1, -1
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li x11, 4095
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# CHECK-EXPAND: lui a1, 1048575
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# CHECK-EXPAND: addiw a1, a1, 1
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li x11, -4095
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# CHECK-EXPAND: lui a2, 1
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li x12, 4096
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# CHECK-EXPAND: lui a2, 1048575
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li x12, -4096
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# CHECK-EXPAND: lui a2, 1
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# CHECK-EXPAND-NEXT: addiw a2, a2, 1
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li x12, 4097
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# CHECK-EXPAND: lui a2, 1048575
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# CHECK-EXPAND: addiw a2, a2, -1
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li x12, -4097
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# CHECK-EXPAND: lui a2, 524288
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# CHECK-EXPAND-NEXT: addiw a2, a2, -1
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li x12, 2147483647
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# CHECK-EXPAND: lui a2, 524288
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# CHECK-EXPAND-NEXT: addiw a2, a2, 1
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li x12, -2147483647
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# CHECK-EXPAND: lui a2, 524288
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li x12, -2147483648
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# CHECK-EXPAND: lui a2, 524288
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li x12, -0x80000000
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# CHECK-EXPAND: addi a2, zero, 1
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# CHECK-EXPAND-NEXT: slli a2, a2, 31
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li x12, 0x80000000
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# CHECK-EXPAND: addi a2, zero, -1
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# CHECK-EXPAND-NEXT: srli a2, a2, 32
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li x12, 0xFFFFFFFF
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# CHECK-EXPAND: addi t0, zero, 1
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# CHECK-EXPAND-NEXT: slli t0, t0, 32
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li t0, 0x100000000
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# CHECK-EXPAND: addi t1, zero, -1
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# CHECK-EXPAND-NEXT: slli t1, t1, 63
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li t1, 0x8000000000000000
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# CHECK-EXPAND: addi t1, zero, -1
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# CHECK-EXPAND-NEXT: slli t1, t1, 63
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li t1, -0x8000000000000000
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# CHECK-EXPAND: lui t2, 9321
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# CHECK-EXPAND-NEXT: addiw t2, t2, -1329
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# CHECK-EXPAND-NEXT: slli t2, t2, 35
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li t2, 0x1234567800000000
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# CHECK-EXPAND: addi t3, zero, 7
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# CHECK-EXPAND-NEXT: slli t3, t3, 36
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# CHECK-EXPAND-NEXT: addi t3, t3, 11
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# CHECK-EXPAND-NEXT: slli t3, t3, 24
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# CHECK-EXPAND-NEXT: addi t3, t3, 15
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li t3, 0x700000000B00000F
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# CHECK-EXPAND: lui t4, 583
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# CHECK-EXPAND-NEXT: addiw t4, t4, -1875
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# CHECK-EXPAND-NEXT: slli t4, t4, 14
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# CHECK-EXPAND-NEXT: addi t4, t4, -947
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# CHECK-EXPAND-NEXT: slli t4, t4, 12
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# CHECK-EXPAND-NEXT: addi t4, t4, 1511
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# CHECK-EXPAND-NEXT: slli t4, t4, 13
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# CHECK-EXPAND-NEXT: addi t4, t4, -272
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li t4, 0x123456789abcdef0
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# CHECK-EXPAND: addi t5, zero, -1
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li t5, 0xFFFFFFFFFFFFFFFF
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# CHECK-EXPAND: lui t6, 262145
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# CHECK-EXPAND-NEXT: slli t6, t6, 1
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li t6, 0x80002000
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# CHECK-EXPAND: lui t0, 262145
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# CHECK-EXPAND-NEXT: slli t0, t0, 2
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li x5, 0x100004000
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# CHECK-EXPAND: lui t1, 4097
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# CHECK-EXPAND-NEXT: slli t1, t1, 20
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li x6, 0x100100000000
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# CHECK-EXPAND: lui t2, 983056
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# CHECK-EXPAND-NEXT: srli t2, t2, 16
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li x7, 0xFFFFFFFFF001
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# CHECK-EXPAND: lui s0, 1044481
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# CHECK-EXPAND-NEXT: slli s0, s0, 12
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# CHECK-EXPAND-NEXT: srli s0, s0, 24
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li x8, 0xFFFFFFF001
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# CHECK-EXPAND: lui s1, 4097
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# CHECK-EXPAND-NEXT: slli s1, s1, 20
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# CHECK-EXPAND-NEXT: addi s1, s1, -3
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li x9, 0x1000FFFFFFFD
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# CHECK-EXPAND: addi a0, zero, -1
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# CHECK-EXPAND-NEXT: slli a0, a0, 36
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# CHECK-EXPAND-NEXT: addi a0, a0, 1
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# CHECK-EXPAND-NEXT: slli a0, a0, 25
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# CHECK-EXPAND-NEXT: addi a0, a0, -1
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li x10, 0xE000000001FFFFFF
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# CHECK-EXPAND: addi a1, zero, -2047
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# CHECK-EXPAND-NEXT: slli a1, a1, 27
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# CHECK-EXPAND-NEXT: addi a1, a1, -1
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# CHECK-EXPAND-NEXT: slli a1, a1, 12
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# CHECK-EXPAND-NEXT: addi a1, a1, 2047
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li x11, 0xFFFC007FFFFFF7FF
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# CHECK-EXPAND: addi a0, zero, 1110
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li a0, %lo(0x123456)
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# CHECK-OBJ-NOALIAS: addi a0, zero, 0
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# CHECK-OBJ: R_RISCV_LO12
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li a0, %lo(foo)
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# CHECK-OBJ-NOALIAS: addi a0, zero, 0
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# CHECK-OBJ: R_RISCV_PCREL_LO12
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li a0, %pcrel_lo(.Lpcrel_hi0)
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.equ CONST, 0x123456
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# CHECK-EXPAND: lui a0, 291
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# CHECK-EXPAND: addiw a0, a0, 1110
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li a0, CONST
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.equ CONST, 0x654321
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# CHECK-EXPAND: lui a0, 1620
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# CHECK-EXPAND: addiw a0, a0, 801
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li a0, CONST
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# CHECK-INST: subw t6, zero, ra
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# CHECK-ALIAS: negw t6, ra
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negw x31, x1
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# CHECK-INST: addiw t6, ra, 0
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# CHECK-ALIAS: sext.w t6, ra
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sext.w x31, x1
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# The following aliases are accepted as input but the canonical form
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# of the instruction will always be printed.
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# CHECK-INST: addiw a2, a3, 4
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# CHECK-ALIAS: addiw a2, a3, 4
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addw a2,a3,4
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# CHECK-INST: slliw a2, a3, 4
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# CHECK-ALIAS: slliw a2, a3, 4
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sllw a2,a3,4
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# CHECK-INST: srliw a2, a3, 4
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# CHECK-ALIAS: srliw a2, a3, 4
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srlw a2,a3,4
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# CHECK-INST: sraiw a2, a3, 4
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# CHECK-ALIAS: sraiw a2, a3, 4
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sraw a2,a3,4
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# CHECK-EXPAND: lwu a0, 0(a1)
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lwu x10, (x11)
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# CHECK-EXPAND: ld a0, 0(a1)
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ld x10, (x11)
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# CHECK-EXPAND: sd a0, 0(a1)
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sd x10, (x11)
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# CHECK-EXPAND: slli a0, a1, 56
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# CHECK-EXPAND: srai a0, a0, 56
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sext.b x10, x11
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# CHECK-EXPAND: slli a0, a1, 48
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# CHECK-EXPAND: srai a0, a0, 48
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sext.h x10, x11
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# CHECK-INST: andi a0, a1, 255
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# CHECK-ALIAS: andi a0, a1, 255
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zext.b x10, x11
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# CHECK-EXPAND: slli a0, a1, 48
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# CHECK-EXPAND: srli a0, a0, 48
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zext.h x10, x11
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# CHECK-EXPAND: slli a0, a1, 32
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# CHECK-EXPAND: srli a0, a0, 32
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zext.w x10, x11
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